SUMMARY: Research Fellow, Invited Auxiliary Professor at ISTAR-IUL, ISCTE, currently researching neuromorphic systems for end-to-end application of machine learning to enhanced living spaces via digital assistance.I am an experienced hands-on innovator and educator, interested in developing new research areas, and applying my creativity to solve new problems by fostering strong interaction between academia and industry with focus on developing research results with practical application, leveraging my industrial experience at an academic research setting.    My recent interests involve the interaction of efficient implementation and application of machine learning/deep neural networks, cloud workloads and cluster systems, application of systems research to large data sets and machine learning analytics, compilers, compilation techniques and (micro) architecture, (processing) system architecture at the node and cluster level, power-efficient computing, heterogeneous processing systems (CPUs, GPUs), with goals of influencing applications, products, and innovation. I foresee potential development of analysis and data mining tools and computing systems to further ISCTE's mission related to natural interaction and communication. I have successfully submitted and received approval for a research project under Horizon-2020 on heterogeneous computing, as part of a consortium with 6 leading European universities, of which I was one of the Principal Investigators for AMD (CHIST-ERA Research Grant. Distributed Heterogeneous Vertically-Integrated Energy-Efficient Data Centres. Total  2M euros , AMD portion  800K euros , Jul 2014.) Recently I've worked on understanding and optimizing cloud applications and cloud workload analysis (MapReduce, Hadoop, GraphLab), focusing on system-level characterization an innovation for power efficient computing and dense servers. In collaboration with researchers at Rice University we have developed efficient acceleration for Hadoop Map-Reduce and Machine Learning applications on GPU accelerated systems. I also investigate efficient implementation of Deep Neural Network algorithms on CPU+GPU accelerated systems and developed novel algorithms for CPU/GPU code migration (speeding up face detection algorithms on APUs), found ways to program multi-core systems and to use GPUs in the cloud, and to use multiple cores to speed up single-thread performance. My current research interests include application and optimization of recurrent neural networks. My previous projects relate to binary translation (enabling many cores by building smaller legacy-free systems, transactional memory performance evaluation, microcode compression(algorithmic research on ways to save microprocessor core space [adopted in two currently-shipping high-volume production microprocessor designs, US$18M savings]) and co-designed architectural features to enable low-power high-single-thread performance for small cores. I am the creator and serve as general chair of the International Workshop on Architectural/Microarchitectural Support for Binary Translation, joint with ISCA (ACM/IEEE International Symposium on Computer Architecture) and CGO. I have 56 U.S. Patents Issued plus more 55 U.S. Patents Pending