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RESUMO: Pesquisador, Professor Auxiliar Convidado do ISTAR-IUL, ISCTE-IUL, atualmente pesquisando sistemas neuromorficos para aplicações de aprendizado de máquina para melhorar espaços de convivência através de assistência digital. Sou um experiente inovador e educador prático, interessado em desenvolver novas pesquisas e aplicar minha criatividade para resolver novos problemas, promovendo forte interação entre a academia e a indústria, com foco no desenvolvimento de resultados de pesquisa com aplicação prática, aplicando minha experiência industrial em um ambiente de pesquisa acadêmica.      Meus interesses recentes envolvem a interação de implementação e aplicação eficiente de aprendizado de máquina / redes neurais profundas, cargas de trabalho de nuvem e sistemas de cluster, aplicação de pesquisa de sistemas a grandes conjuntos de dados e análise de aprendizado de máquina, compiladores, técnicas de compilação e (micro) arquitetura. arquitetura do sistema no nível do nó e do cluster, computação com uso eficiente de energia, sistemas de processamento heterogêneos (CPUs, GPUs), com objetivos de influenciar aplicativos, produtos e inovação. Prevejo o potencial desenvolvimento de ferramentas de análise e mineração de dados e sistemas de computação para promover a missão do ISTAR-IUL relacionada à interação e comunicação naturais. Submeti com sucesso e recebi a aprovação de um projeto de pesquisa sob o  programa Horizonte-2020 em computação heterogênea, como parte de um consórcio com seis universidades européias, das quais eu fui um dos principais pesquisadores da AMD (Projeto CHIST-ERA. Total de 2 milhões de euros, parte da AMD 800K euros, julho de 2014.) Recentemente, trabalhei no entendimento e otimização de aplicativos em nuvem e análise de carga de trabalho em nuvem (MapReduce, Hadoop, GraphLab), focando a nível de sistema. Em colaboração com pesquisadores da Rice University, desenvolvemos uma aceleração eficiente para aplicativos Hadoop Map-Reduce e Machine Learning em sistemas acelerados por GPU. Eu também investiguei a implementação eficiente de algoritmos Deep Neural Network em sistemas acelerados CPU + GPU e desenvolvi novos algoritmos para migração de código CPU / GPU (acelerando algoritmos de detecção de face em APUs), encontrei maneiras de programar sistemas multi-core e usar GPUs no nuvem e usar vários núcleos para acelerar o desempenho de encadeamento único. Meus interesses atuais de pesquisa incluem aplicação e otimização de redes neurais. Meus projetos anteriores estão relacionados à tradução binária (habilitando muitos núcleos construindo sistemas legados menores, avaliação de desempenho de memória transacional, compactação de microcódigo (pesquisa algorítmica sobre formas de economizar espaço de microprocessador [adotada em dois projetos de microprocessador de produção de alto volume) Economias de US $ 18M] e características arquitetônicas co-projetadas para possibilitar um desempenho de alta potência e thread única para núcleos pequenos. Eu sou o criador e atuo como presidente geral do Workshop Internacional de Suporte Arquitetônico / Microarquitetural para Tradução Binária, com ISCA (ACM / IEEE Simpósio Internacional de Arquitetura de Computadores) e CGO. Tenho 56 patentes americanas emitidas e mais outras 55 patentes americanas pendentes
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Identification

Personal identification

Full name
Mauricio Breternitz Jr

Citation names

  • Jr, Mauricio
  • M.Breternitz

Author identifiers

Ciência ID
F01D-62A9-B4CD
ORCID iD
0000-0003-1752-6255
Google Scholar ID
pnmGA74AAAAJ

Websites

Knowledge fields

  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Computer Hardware and Architecture
  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics
  • Exact Sciences - Computer and Information Sciences

Languages

Language Speaking Reading Writing Listening Peer-review
English Proficiency (C2) Proficiency (C2) Proficiency (C2) Proficiency (C2) Proficiency (C2)
Portuguese (Mother tongue)
Education
Degree Classification
1991/12/31
Concluded
 Ph.D.in Electrical and Computer Engineering (Doutoramento)
Carnegie Mellon University, Portugal
Affiliation

Science

Category
Host institution 		Employer
2019/06/01 - Current Principal Investigator (Research) ISCTE-Instituto Universitário de Lisboa, Portugal
ISCTE-Instituto Universitário de Lisboa Centro de Investigação em Ciências da Informação Tecnologias e Arquitetura, Portugal
2010/02/01 - 2017/03/31 Principal Investigator (Research) Advanced Micro Devices Inc Research, United States
AMD Research (Advanced Micro Devices), United States
2002/02/01 - 2010/01/31 Principal Investigator (Research) Intel Labs, United States
Intel Labs, United States

Teaching in Higher Education

Category
Host institution 		Employer
2018/06/01 - 2019/05/31 Invited Associate Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 - 2018 Invited Assistant Professor (University Teacher) ISCTE-Instituto Universitário de Lisboa, Portugal
Projects

Contract

Designation Funders
2021/01/25 - 2023/01/24 AI-based mobile applications for public health response
DSAIPA/AI/0122/2020
Researcher
ISCTE-Instituto Universitário de Lisboa Centro de Investigação em Ciências da Informação Tecnologias e Arquitetura, Portugal

Instituto de Telecomunicações, Portugal

Association For Research, Development Of Medical School, Portugal
FCT
Ongoing
2017/01/01 - 2018/12/31 ILUMI
UID/Multi/04466/2016
Researcher
ISCTE-Instituto Universitário de Lisboa Centro de Investigação em Ciências da Informação Tecnologias e Arquitetura, Portugal
 FCT
Concluded
Outputs

Publications

Book
  1. M.Breternitz; Cohn, R.; Altman, E.; Wu, Youfeng. AMAS-BT foreword. 2012.
    Published
  2. M.Breternitz; Cohn, R.; Altman, E.; Wu, Youfeng. AMAS-BT foreword. 2011.
    Published
  3. Wang, Cheng; Thottethodi, Mithuna S; Kim, Ho-Seop; Nair, Sreekumar R; M.Breternitz; Ying, Zhiwei; Wu, Youfeng. StarDBT: An efficient multi-platform dynamic binary translation system. 2007.
    Published • 10.1007/978-3-540-74309-5_3
Conference paper
  1. John, L. K.; França, F. M. G.; Mitra, S.; Susskind, Z.; Lima, P. M. V.; Miranda, I. D. S.; John, E. B.; Dutra, D. L. C.; Breternitz Jr., M.. "Dendrite-inspired computing to improve resilience of neural networks to faults in emerging memory technologies". Paper presented in 2023 IEEE International Conference on Rebooting Computing (ICRC), San Diego, CA, USA, 2024.
    Published • 10.1109/ICRC60800.2023.10386729
  2. Miranda, I. D. S.; Arora, A.; Susskind, Z.; Souza, J. S. A.; Jadhao, M. P.; Villon, L. A. Q.; Dutra, D. L. C.; et al. "COIN: Combinational Intelligent Networks". Paper presented in 2023 IEEE 34th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Porto, Portugal, 2023.
    Published • 10.1109/ASAP57973.2023.00016
  3. Susskind, Z.; Arora, A.; Bacellar, A.; Dutra, D. L. C.; Miranda, I. D. S.; Breternitz Jr., M.; Lima, P. M. V.; França, F. M. G.; John, L. K.. "An FPGA-based weightless neural network for edge network intrusion detection". Paper presented in FPGA '23: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey CA USA, 2023.
    Published • 10.1145/3543622.3573140
  4. Napoli, O. O.; Almeida, A. M. de.; Dias, J. M. S.; Rosário, L. B.; Borin, E.; Breternitz Jr, M.. "Efficient knowledge aggregation methods for weightless neural networks". Paper presented in Proceedings of the 31th European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning (ESANN 2023), Bruges, Belgium, 2023.
    Published • 10.14428/esann/2023.ES2023-123
  5. Bacellar, A. T. L.; Susskind, Z.; Villon, L. A. Q. ; Miranda, I. D. S.; Araújo, L. S. de.; Dutra, D. L. C.; Breternitz Jr, M.; et al. "Distributive thermometer: A new unary encoding for weightless neural networks". Paper presented in ESANN 2022 proceedings, 2022.
    Published • 10.14428/esann/2022.ES2022-94
  6. Susskind, Z.; Bacellar, A. T. L.; Arora, A.; Villon, L. A. Q.; Mendanha, R.; Araújo, L. S. de.; Dutra, D. L. C.; et al. "Pruning weightless neural networks". Paper presented in ESANN 2022 proceedings, 2022.
    Published • 10.14428/esann/2022.ES2022-55
  7. Villon, L. A. Q.; Susskind, Z.; Bacellar, A. T. L.; Miranda, I. D. S.; Araújo, L. S. de.; Lima, P. M. V.; Breternitz Jr, M.; et al. "A WiSARD-based conditional branch predictor". Paper presented in ESANN 2022 proceedings, 2022.
    Published • 10.14428/esann/2022.ES2022-65
  8. Miranda, I. D. S.; Arora, A.; Susskind, Z.; Villon, L. A. Q.; Katopodis, R. F.; Dutra, D. L. C.; Araújo, L. S. de.; et al. "LogicWiSARD: Memoryless synthesis of weightless neural networks". Paper presented in 2022 IEEE 33rd International Conference on Application-specific Systems, Architectures and Processors (ASAP), Gothenburg, Sweden, 2022.
    Published • 10.1109/ASAP54787.2022.00014
  9. Susskind, Z.; Arora, A.; Miranda, I. D. S.; Villon, L. A. Q.; Katopodis, R. F.; Araújo, L. S. de.; Dutra, D. L. C.; et al. "Weightless Neural Networks for efficient edge inference". Paper presented in PACT '22: Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, Chicago, Illinois, 2022.
    Published • 10.1145/3559009.3569680
  10. Felipe Franca; M.Breternitz; Leandro Araujo. "Memory Efficient Weightless Neural Network using Bloom Filter". Paper presented in 27 th European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, --, 2019.
    Published
  11. Silva, H.; Resende, R.; Breternitz, M.. "Mixed reality application to support infrastructure maintenance". Paper presented in 2nd International Young Engineers Forum, YEF-ECE 2018, Costa da Caparica, 2018.
    Published • 10.1109/YEF-ECE.2018.8368938
  12. Lebeane, M.; Hamidouche, K.; Benton, B.; Breternitz, M.; Reinhardt, S. K.; John, L. K.. "ComP-Net: command processor networking for efficient intra-kernel communications on GPUs". Paper presented in Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT, Limassol, 2018.
    Published • 10.1145/3243176.3243179
  13. Lebeane, Michael W; Khaled Hamidouche; Brad Benton; M.Breternitz; Steven K. Reinhardt; Lizy K. John. "GPU triggered networking for intra-kernel communications". Paper presented in International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2017, Denver, 2017.
    Published • 10.1145/3126908.3126950
  14. Benedicto, C.; Rodrigues, I. L.; Tygel, M.; Breternitz, M.; Borin, E.. "Harvesting the computational power of heterogeneous clusters to accelerate seismic processing". Paper presented in Global Meeting Expanded Abstracts, Rio de Janeiro, 2017.
    Published • 10.1190/sbgf2017-070
  15. Borin, Edson; Benedicto, Caian; Rodrigues, Ian L; Pisani, Flávia; Tygel, Martin; M.Breternitz. "PY-PITS: A Scalable Python Runtime System for the Computation of Partially Idempotent Tasks". Paper presented in Computer Architecture and High Performance Computing Workshops (SBAC-PADW), 2016 International Symposium on, 2016.
    Published • 10.1109/SBAC-PADW.2016.10
  16. Lebeane, Michael W; Brandon Potter; Abhisek Pan; Alexandru Dutu; Vinay Agarwala; Wonchan Lee; Majeti, Deepak; et al. "Extended Task Queuing: Active Messages for Heterogeneous Systems". 2016.
    10.1109/SC.2016.79
  17. Borin, Edson; Rodrigues, Ian L; Novo, Alber T; Sacramento, João D; M.Breternitz; Tygel, Martin. "Efficient and Fault Tolerant Computation of Partially Idempotent Tasks". Paper presented in 14th International Congress of the Brazilian Geophysical Society & EXPOGEF, Rio de Janeiro, Brazil, 3-6 August 2015, 2015.
    Published • 10.1190/sbgf2015-072
  18. Dias, J.; Zhu, Maohua; Zhou, Zhitao; Zhang, Feng; Lin, Zhen; Zhang, Qianfeng; M.Breternitz. "Implementation and evaluation of Deep Neural Networks (DNN) on mainstream heterogeneous systems". Paper presented in Proceedings of 5th Asia-Pacific Workshop on Systems, APSYS 2014, 2014.
    Published • 10.1145/2637166.2637229
  19. Gu, Junli; Zhu, Maohua; Zhou, Zhitao; Zhang, Feng; Lin, Zhen; Zhang, Qianfeng; M.Breternitz. "Implementation and evaluation of deep neural networks (dnn) on mainstream heterogeneous systems". Paper presented in Proceedings of 5th Asia-Pacific Workshop on Systems, 2014.
    Published
  20. Pedronette, Daniel Carlos Guimaraes; Torres, Ricardo da S; Borin, Edson; M.Breternitz. "Image re-ranking acceleration on GPUs". Paper presented in Computer Architecture and High Performance Computing (SBAC-PAD), 2013 25th International Symposium on, 2013.
    Published • 10.1109/ISPA.2012.21
  21. Grossman, Max; M.Breternitz; Sarkar, Vivek. "Hadoopcl: Mapreduce on distributed heterogeneous platforms through seamless integration of hadoop and opencl". Paper presented in Parallel and Distributed Processing Symposium Workshops \& PhD Forum (IPDPSW), 2013 IEEE 27th International, 2013.
    Published • 10.1109/IPDPSW.2013.246
  22. M.Breternitz; Lowery, Keith; Charnoff, Anton; Kaminski, Patryk; Piga, Leonardo. "Cloud Workload Analysis with SWAT". Paper presented in Computer Architecture and High Performance Computing (SBAC-PAD), 2012 IEEE 24th International Symposium on, 2012.
    Published • 10.1109/SBAC-PAD.2012.13
  23. Borin, Edson; Wu, Youfeng; M.Breternitz; Wang, Cheng. "LAR-CC: Large atomic regions with conditional commits". Paper presented in Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization, --, 2011.
    Published • 10.1109/CGO.2011.5764674
  24. Borin, Edson; Araujo, Guido; M.Breternitz; Wu, Youfeng. "Structure-Constrained Microcode Compression". Paper presented in Computer Architecture and High Performance Computing (SBAC-PAD), 2011 23rd International Symposium on, 2011.
    Published • 10.1109/SBAC-PAD.2011.32
  25. Borin, Edson; Wu, Youfeng; Wang, Cheng; Liu, Wei; M.Breternitz; Thottethodi, Mithuna S; Natanzon, Esfir; Rotem, Shai; Rosner, Roni. "TAO: Two-level atomicity for dynamic binary optimizations". 2010.
    Published • 10.1145/1772954.1772959
  26. Borin, Edson; Wu, Youfeng; Wang, Cheng; Liu, Wei; M.Breternitz; Hu, Shiliang; Natanzon, Esfir; Rotem, Shai; Rosner, Roni. "TAO: two-level atomicity for dynamic binary optimizations". Paper presented in Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization, 2010.
    Published
  27. M.Breternitz; Loh, Gabriel H; Black, Bryan; Jeffrey, P Rupley II; Sassone, Peter G; Attrot, Wesley; Wu, Youfeng. "A segmented bloom filter algorithm for efficient predictors". Paper presented in Computer Architecture and High Performance Computing, 2008. SBAC-PAD'08. 20th International Symposium on, 2008.
    Published • 10.1109/SBAC-PAD.2008.24
  28. M.Breternitz. "Message from the general chair". Paper presented in Proceedings of the 2007 IEEE International Symposium on Workload Characterization, IISWC, 2007.
    Published • 10.1109/IISWC.2007.4362169
  29. Wu, Youfeng; M.Breternitz; Ying, Victor. "Impacts of multiprocessor configurations on workloads in bioinformatics". 2007.
    Published • 10.1109/SBAC-PAD.2007.25
  30. Borin, Edson; M.Breternitz; Wu, Youfeg; Araujo, Guido. "Clustering-based microcode compression". Paper presented in Computer Design, 2006. ICCD 2006. International Conference on, 2007.
    Published
  31. Wang, Cheng; Hu, Shiliang; Kim, Ho-seop; Nair, Sreekumar R; M.Breternitz; Ying, Zhiwei; Wu, Youfeng. "StarDBT: an efficient multi-platform dynamic binary translation system". Paper presented in Asia-Pacific Conference on Advances in Computer Systems Architecture, 2007.
    Published
  32. Wu, Youfeng; M.Breternitz; Ying, Victor. "Impacts of Multiprocessor Configurations on Workloads in Bioinformatics". Paper presented in Computer Architecture and High Performance Computing, 2007. SBAC-PAD 2007. 19th International Symposium on, 2007.
    Published
  33. Borin, Edson; M.Breternitz; Wu, Youfeg; Araujo, Guido. "Clustering-based microcode compression". Paper presented in IEEE International Conference on Computer Design, ICCD 2006, 2006.
    Published • 10.1109/ICCD.2006.4380816
  34. M.Breternitz; Hum, Herbert; Peri, Ramesh; Pickett, Jay; Wu, Youfeng. "Enhanced code density of embedded CISC processors with echo technology". Paper presented in Hardware/Software Codesign and System Synthesis, 2005. CODES+ ISSS'05. Third IEEE/ACM/IFIP International Conference on, 2005.
    Published • 10.1145/1084834.1084878
  35. Wu, Youfeng; M.Breternitz; Devor, T.. "Continuous trip count profiling for loop optimizations in two-phase dynamic binary translators". Paper presented in Proceedings - Eighth Workshop on Interaction between Compilers and Computer Architectures, INTERACT-8 2004, 2004.
    Published
  36. Wu, Youfeng; M.Breternitz; Quek, Justin; Etzion, Orna; Fang, Jesse. "The accuracy of initial prediction in two-phase dynamic binary translators". 2004.
    Published
  37. Wu, Youfeng; M.Breternitz; Quek, Justin; Etzion, Orna; Fang, Jesse. "The accuracy of initial prediction in two-phase dynamic binary translators". Paper presented in Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, 2004.
    Published
  38. Wu, Youfeng; M.Breternitz; Hum, Herbert; Peri, Ramesh; Pickett, Jay. "Echo Techology (ET) for memory constrained CISC processors". Paper presented in Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES), 2004.
    Published
  39. Wu, Y.; Breternitz, M.; Quek, J.; Etzion, O.; Fang, J.. "The accuracy of initial prediction in two-phase dynamic binary translators". 2004.
  40. M.Breternitz; Hum, Herbert; Kumar, Sanjeev. "Compilation, architectural support, and evaluation of SIMD graphics pipeline programs on a general-purpose CPU". Paper presented in Parallel Architectures and Compilation Techniques, 2003. PACT 2003. Proceedings. 12th International Conference on, 2003.
    Published • 10.1109/PACT.2003.1238010
  41. M.Breternitz; Smith, Roger A. "Enhanced compression techniques to simplify program decompression and execution". Paper presented in Computer Design: VLSI in Computers and Processors, 1997. ICCD'97. Proceedings., 1997 IEEE International Conference on, 1997.
    Published • 10.1109/ICCD.1997.628865
  42. Stewart, K; Butt, F; Sarkisian, D; M.Breternitz. "The Motorola PowerPC/sup TM/PEEK profiler". Paper presented in Performance, Computing, and Communications Conference, 1997. IPCCC 1997., IEEE International, 1997.
    Published • 10.1109/PCCC.1997.581537
  43. Stewart, Katherine; Butt, Farooq; Sarkisian, Drew; M.Breternitz. "Motorola PowerPCTM PEEK profiler". Paper presented in IEEE International Performance, Computing & Communications Conference, Proceedings, 1997.
    Published
  44. M.Breternitz. "Motorola PowerPC Migration Tools-emulation and translation". Paper presented in Compcon'96.'Technologies for the Information Superhighway'Digest of Papers, 1996.
    Published • 10.1109/CMPCON.1996.501761
  45. M.Breternitz. "Design tradeoffs and experience with Motorola PowerPC migration tools". Paper presented in Computer Design: VLSI in Computers and Processors, 1996. ICCD'96. Proceedings., 1996 IEEE International Conference on, 1996.
    Published • 10.1109/ICCD.1996.563571
  46. Simons, Barbara; Sarkar, Vivek; M.Breternitz; Lai, Michael. "An optimal asynchronous scheduling algorithm for software cache consistency". 1994.
    10.1109/hicss.1994.323233
  47. M.Breternitz; Shen, John Paul. "Implementation optimization techniques for architecture synthesis of application-specific processors". Paper presented in Proceedings of the 24th annual international symposium on Microarchitecture, 1991.
    Published • 10.1145/123465.123488
  48. M.Breternitz; Shen, John Paul. "Architecture synthesis of high-performance application-specific processors". Paper presented in 27th ACM/IEEE Design Automation Conference, Orlando, FL, USA, 1990.
    Published • 10.1109/DAC.1990.114915
  49. M.Breternitz; Alex Nicolau. "Tradeoffs between Pipelining and Multiple Functional Units in Fine-grain Parallelism Exploitation". Paper presented in , Fourth International Conference on Supercomputing and Third World Supercomputer Exhibition, Santa Clara, CA, 1989.
    Published
  50. M.Breternitz; Shen, John Paul. "Organization of array data for concurrent memory access". Paper presented in Proceedings of the 21st annual workshop on Microprogramming and microarchitecture, --, 1988.
    Published
  51. Wolfe, Andrew; M.Breternitz; Stephens, Chriss; Ting, AL; Kirk, DB; Bianchini Jr, Ronald P; Shen, John Paul. "The white dwarf: a high-performance application-specific processor". Paper presented in ACM SIGARCH Computer Architecture News, 1988.
    Published • 10.1145/633625.52425
Journal article
  1. Villon, L. A. Q.; Susskind, Z.; Bacellar, A. T. L.; Miranda, I. D. S.; Araújo, L. S. de.; Lima, P. M. V.; Breternitz Jr., M.; et al. "A conditional branch predictor based on weightless neural networks". Neurocomputing 555 (2023): https://www.sciencedirect.com/journal/neurocomputing.
    Published • 10.1016/j.neucom.2023.126637
  2. Susskind, Z.; Arora, A.; Miranda, I. D. S.; Bacellar, A. T. L.; Villon, L. A. Q.; Katopodis, R. F.; Araújo, L. S. de; et al. "ULEEN: A novel architecture for ultra low-energy edge neural networks". ACM Transactions on Architecture and Code Optimization 20 4 (2023): https://dl.acm.org/doi/10.1145/3629522.
    Published • 10.1145/3629522
  3. Rosario, V. M. Do; Breternitz, M.; Borin, E.. "Efficiency and scalability of Multi-Lane Capsule Networks (MLCN)". Journal of Parallel and Distributed Computing 155 (2021): 63-73. https://www.sciencedirect.com/journal/journal-of-parallel-and-distributed-computing.
    Published • 10.1016/j.jpdc.2021.04.010
  4. Martins do Rosário, V. ; Silva, A. F. Da; Camacho, T. A. S.; Breternitz, M.; Borin, E.; napoli, O. O.. "Smart selection of optimizations in dynamic compilers". Concurrency and Computation: Practice and Experience 33 18 (2021): https://onlinelibrary.wiley.com/journal/15320634.
    Published • 10.1002/cpe.6089
  5. Pisani, Flávia; Lucas Pascotti Valem; Pedronette, Daniel Carlos Guimaraes; Torres, Ricardo da S; Borin, Edson; M.Breternitz. "A unified model for accelerating unsupervised iterative re-ranking algorithms". Concurrency and Computation: Practice and Experience 32 14 (2020): https://onlionelibrary.wiley.com/.
    Published • 10.1002/cpe.5702
  6. M.Breternitz; Leandro Araujo; L.Verona; F.Rangel; F.Firmino; D.Menasche; W.Caarls; et al. "Weightless neural networks as memory segmented bloom filters". Neurocomputing Volume 416 27 Novembe (2020): https://www.journals.elsevier.com/neurocomputing.
    Published • 10.1016/j.neucom.2020.01.115
  7. Vanderson Martins do Rosario; Borin, Edson; Breternitz, M.. "The multi-lane capsule network (MLCN)". IEEE Signal Processing Letters 26 7 (2019): 1-1. https://ieeexplore.ieee.org/document/8709729.
    Published • 10.1109/LSP.2019.2915661
  8. Grossman, M.; Breternitz, M.; Sarkar, V.. "Hadoopcl2: motivating the design of a distributed, heterogeneous programming system with machine-learning applications". IEEE Transactions on Parallel and Distributed Systems 27 3 (2016): 762-775. http://ieeexplore.ieee.org/document/7064791/.
    Published • 10.1109/TPDS.2015.2414943
  9. Piga, L.; Bergamaschi, R. A.; Breternitz, M.; Rigo, S.. "Adaptive global power optimization for Web servers". The Journal of Supercomputing 68 3 (2014): 1088-1112. https://link.springer.com/article/10.1007/s11227-014-1141-x.
    Published • 10.1007/s11227-014-1141-x
  10. Borin, E.; Araujo, G.; Breternitz, M.; Wu, Y.. "Microcode compression using structured-constrained clustering". International Journal of Parallel Programming 42 1 (2014): 140-164. https://link.springer.com/article/10.1007%2Fs10766-012-0206-9.
    Published • 10.1007/s10766-012-0206-9
  11. M.Breternitz; Keckler, Stephen W; McKinley, Kathryn S. "Efficient adaptation of multiple microprocessor resources for energy reduction using dynamic optimization". Proceedings of the Annual Hawaii International Conference on System Sciences (2005):
    Published
  12. Bernstein, D.; Breternitz, M.; Gheith, A. M.; Mendelson, B.. "Solutions and debugging for data consistency in multiprocessors with noncoherent caches". International Journal of Parallel Programming 23 1 (1995): 83-103. https://link.springer.com/article/10.1007%2FBF02577785.
    Published • 10.1007/BF02577785
  13. Sarkar, B. S. V.; Sarkar, V.; Breternitz, M.; Lai, M.. "An optimal asynchronous scheduling algorithm for software cache consistency". -- (1994): http://ieeexplore.ieee.org/document/323233/.
    10.1109/HICSS.1994.323233

Intellectual property

Patent
  1. Jr, Mauricio. 2017. "POWER MANAGEMENT OF INTERACTIVE WORKLOADS DRIVEN BY DIRECT AND INDIRECT USER FEEDBACK".

Other

Other output
  1. Federated AI for Health. A standards body for AI. 2023. M.Breternitz; de Almeida, A.. https://mpai.community/news/mpai-events/a-standards-body-for-ai/.
  2. Architectural Predictors using Weightless Neural Networks. Seminar - AMD Research - Advanced Micro Devices - Oct 28. 2022. M.Breternitz. https://www.amd.com/en/corporate/research.
  3. An intelligent systems approach for early illness symptoms detection: AIM (your) Health. 1a Conferência de Saúde Societal. 2022. de Almeida, A.; M.Breternitz; napoli, O. O.. https://iscte-saude.iscte-iul.pt.
  4. Weightless Neural Networks - a lightweight approach for efficient Machine Learning. Seminar Series - CMM Center for Mathematical Morphology- Paris Tech. 2022. M.Breternitz; Felipe Franca; Priscila Lima. https://interne.cmm.minesparis.psl.eu/wiki/doku.php/seminaires/start.
  5. Ciencia na Industria. Computacao Podcast. 2020. M.Breternitz. https://computacaopodcast.com.br/.
  6. Neuromorphic Computing: Key Concepts, Status, Promise and Research Challenges. LMCAD Seminar. 2020. M.Breternitz. https://lmcad.ic.unicamp.br/news.html.
  7. Introducao `a Arquitetura de Computadores. Aula convidada IAC DEI Instituto Superior Tecnico. 2020. M.Breternitz. https://fenix.tecnico.ulisboa.pt/disciplinas/IAC45179577/2020-2021/1-semestre.
  8. Efficiency and Scalability of Multi-Lane Capsule Networks (MLCN). CIENCIA 2019 Encontro com a Ciencia e Tecnologia em Portugal. 2019. M.Breternitz. https://ciencia.iscte-iul.pt/publications/efficiency-and-scalability-of-multi-lane-capsule-networks-mlcn-/61916?lang=en.
    10.1109/SBAC-PAD.2019.00034
  9. e2eML: High Performance, Power Efficient Application of End to End Machine Learning Systems. NII Shonan Meeting Seminar No. 134 ADVANCES IN HETEROGENEOUS COMPUTING FROM HARDWARE TO SOFTWARE. 2018. M.Breternitz. https://shonan.nii.ac.jp/seminars/134/.
  10. ASR Automatic Speech Recognition for European Portuguese with the Kaldi Framework. CIENCIA 2018 Encontro com a Ciencia e Tecnologia em Portugal. 2018. M.Breternitz; Dias, J.; Pedro Santos. http://www.encontrociencia.pt/2018/home/.
  11. POWER-AWARE WORK STEALING. --. 2017. Lebeane, Michael W; Majeti, Deepak; M.Breternitz. https://ciencia.iscte-iul.pt/publications/power-aware-work-stealing/37661?lang=en.
  12. System and method for modifying a hardware configuration of a cloud computing system. --. 2016. M.Breternitz; Lowery, Keith A; Kaminski, Patryk; Chernoff, Anton.
  13. Workload partitioning among heterogeneous processing nodes. --. 2016. M.Breternitz; Frost, Gary.
  14. Combined dynamic and static power and performance optimization on data centers. --. 2016. M.Breternitz; Piga, Leonardo; Kaminski, Patryk.
  15. Mechanisms to bound the presence of cache blocks with specific properties in caches. --. 2016. Eckert, Yasuko; Loh, Gabriel H; M.Breternitz; O'connor, James M; Manne, Srilatha; Jayasena, Nuwan S; Thottethodi, Mithuna S.
  16. System and method for configuring a cloud computing system with a synthetic test workload. --. 2015. M.Breternitz; Lowery, Keith A; Kaminski, Patryk; Chernoff, Anton.
  17. Processing device with independently activatable working memory bank and methods. --. 2015. Thottethodi, Mithuna; Loh, Gabriel; M.Breternitz; O'connor, James; Eckert, Yasuko.
  18. Power-efficient nested map-reduce execution on a cloud of heterogeneous accelerated processing units. --. 2015. Kaminski, Patryk; M.Breternitz; Frost, Gary R; Harle, Christophe.
  19. Instruction boundary prediction for variable length instruction set. --. 2015. M.Breternitz; Wu, Youfeng; Sassone, Peter; Mason, James; Phansalkar, Aashish; Vijayan, Balaji.
  20. Thread assignment for power and performance efficiency using multiple power states. --. 2015. M.Breternitz; Piga, Leonardo.
  21. Semi-static power and performance optimization of data centers. --. 2015. M.Breternitz; Piga, Leonardo.
  22. Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region. --. 2015. M.Breternitz; Wu, Youfeng; Wang, Cheng; Borin, Edson; Hu, Shiliang; Zilles, Criag B.
  23. Selecting a resource from a set of resources for performing an operation. --. 2015. Beckmann, Bradford M; Thottethodi, Mithuna S; O'connor, James M; M.Breternitz; Hsu, Lisa R; Loh, Gabriel H; Eckert, Yasuko.
  24. Automatic load balancing for heterogeneous cores. --. 2014. M.Breternitz; Kaminski, Patryk; Lowery, Keith; Chernoff, Anton.
  25. Automatic kernel migration for heterogeneous cores. --. 2014. M.Breternitz; Kaminski, Patryk; Lowery, Keith; Chernoff, Anton; Ju, Dz-ching.
  26. Processor with garbage-collection based classification of memory. --. 2014. Loh, Gabriel H; M.Breternitz.
  27. Nvram-aware data processing system. --. 2014. Blagodurov, Sergey; Loh, Gabriel H; M.Breternitz.
  28. Benchmark generation using instruction execution information. --. 2013. M.Breternitz; Chernoff, Anton; Lowery, Keith A.
  29. Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region. --. 2013. M.Breternitz; Wu, Youfeng; Wang, Cheng; Borin, Edson; Hu, Shiliang; Zilles, Craig B.
  30. Tracking Non-Native Content in Caches. --. 2012. Loh, Gabriel H; Thottehodi, Mithuna S; Eckert, Yasuko; O'connor, James M; M.Breternitz; Beckmann, Bradford M; Jayasena, Nuwan.
  31. Compressing and accessing a microcode ROM. --. 2012. Wu, Youfeng; Kim, Sangwook; M.Breternitz; Hum, Herbert.
  32. System and method for emulating a desired network configuration in a cloud computing system. --. 2012. M.Breternitz; Lowery, Keith A; Kaminski, Patryk; Chernoff, Anton.
  33. Tracking memory bank utility and cost for intelligent power up decisions. --. 2012. M.Breternitz; O'connor, James M; Loh, Gabriel H; Eckert, Yasuko; Thottethodi, Mithuna; Manne, Srilatha; Beckmann, Bradford M.
  34. On-demand emulation via user-level exception handling. --. 2012. Kim, Ho-Seop; M.Breternitz; Wu, Youfeng.
  35. Branch removal by data shuffling. --. 2011. M.Breternitz; Kaminski, Patryk; Lowery, Keith.
  36. Accelerating execution of compressed code. --. 2011. Borin, Edson; M.Breternitz; Bone, Nir; Avni, Shlomo.
  37. Two-pass MRET trace selection for dynamic optimization. --. 2010. Wang, Cheng; Zheng, Bixia; Kim, Ho-Seop; M.Breternitz; Wu, Youfeng.
  38. Dynamic optimization for conditional commit. --. 2010. Wang, Cheng; Borin, Edson; Wu, Youfeng; Hu, Shiliang; Liu, Wei; M.Breternitz.
  39. Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints. --. 2010. Zheng, Bixia; Wang, Cheng; Kim, Ho-Seop; M.Breternitz; Wu, Youfeng.
  40. Apparatus, method, and system for improving power, performance efficiency by coupling a first core type with a second core type. --. 2010. Wu, Youfeng; Hu, Shiliang; Borin, Edson; Wang, Cheng; M.Breternitz; Liu, Wei.
  41. Method and system for reducing program code size. --. 2010. Wu, Youfeng; M.Breternitz.
  42. Efficient bloom filter. --. 2009. M.Breternitz; Wu, Youfeng; Sassone, Peter G; Jeffrey, P Rupley II; Attrot, Wesley; Black, Bryan.
  43. Continuous trip count profiling for loop optimizations in two-phase dynamic binary translators. --. 2008. Wu, Youfeng; M.Breternitz. https://ciencia.iscte-iul.pt/publications/continuous-trip-count-profiling-for-loop-optimizations-in-two-phase-dynamic-binary-translators/37721?lang=en.
    10.1109/INTERA.2004.1299505
  44. Efficient execution and emulation of bit scan operations. --. 2008. M.Breternitz; Wu, Youfeng; Abir, Tal.
  45. Genetic algorithm for microcode compression. --. 2008. Wu, Youfeng; M.Breternitz.
  46. Compressing microcode. --. 2006. Hum, Herbert; M.Breternitz; Wu, Youfeng; Kim, Sangwook.
  47. Method for key escrow in a communication system and apparatus therefor. --. 2004. Smith, Roger A; M.Breternitz.
  48. Method and data processing system for using quick decode instructions. --. 2003. M.Breternitz.
  49. Method and apparatus for compression, decompression, and execution of program code. --. 2002. M.Breternitz; Smith, Roger A.
  50. Method and apparatus for compression, decompression, and execution of program code. --. 2001. M.Breternitz; Smith, Roger A.
  51. Data allocation into multiple memories for concurrent access. --. 1999. M.Breternitz.
  52. Method and system for efficient instruction execution in a data processing system having multiple prefetch units. --. 1998. M.Breternitz.
  53. Method and System for Managing Cache Memory Utilizing Multiple Hash Functikons. U.S.Patent Office. 1997. M.Breternitz. http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=5659699.
  54. Method and system for efficiently fetching variable-width instructions in a data processing system having multiple prefetch units. U.S.Patent Office. 1997. M.Breternitz. http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=5634025.
  55. Redundant load elimination on optimizing compilers. U.S.Patent Office. 1996. M.Breternitz. http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=5537620.
  56. Compiler solutions for the stale-data and false-sharing problems. Technical Report 03.466 IBM Santa Teresa Laboratory. 1993. M.Breternitz; Lai, Michael; Sarkar, Vivek; Simons, Barbara. https://ciencia.iscte-iul.pt/publications/compiler-solutions-for-the-stale-data-and-false-sharing-problems/37684?lang=en.
  57. Architecture Synthesis of High Performance Application-Specific Processors. PhD Thesis:Architecture synthesis of high-performance application-specific processors. 1991. M.Breternitz. http://homepages.cae.wisc.edu/~ece734/references/breternitz91.pdf.
    10.5281/zenodo.1035864
  58. Alocação estruturada de registradores atraves de coloração de grafos. Tese de Mestrado em Ciencias da Computacao. 1984. M.Breternitz. http://repositorio.unicamp.br/bitstream/REPOSIP/276016/1/BreternitzJunior_Mauricio_M.pdf.
Activities

Supervision

Thesis Title
Role 		Degree Subject (Type)
Institution / Organization
2020/11/30 - Current Computational techniques to aid the diagnosis of left ventricle diseases
Co-supervisor of João Henrique Marques Silva
ISCTE-Instituto Universitário de Lisboa, Portugal
2020/11/30 - Current Medical Image classification with Machine Learning : Left Heart disease diagnosis
Co-supervisor of António Maria Sousa Gomes Neto
ISCTE-Instituto Universitário de Lisboa, Portugal
2020/09/08 - Current my Human Brain Project: A Model-free, Probabilistic Policy, Continuous State and Action Spaces, Sparse Reward Reinforcement Learning algorithm on a Graph representation to simulate Human Brain Reasoning
Supervisor of José António Guerreiro Nunes Sanches Salvador
ISCTE-Instituto Universitário de Lisboa, Portugal
2020/01/01 - Current Code Generation for an Educational Processor based on LLVM
Supervisor of Pedro Santos
 Computer Science (Master)
IST Instituto Superior Tecnico - MEIC, Portugal
2017/12/06 - Current Classificação e segmentação de culturas a partir de imagens de satélite
Co-supervisor of João Fernando Bispo Serrano
ISCTE-Instituto Universitário de Lisboa, Portugal
2020/01/01 - 2021/12/31 Code Generation for an Educational Processor based on LCC
Supervisor of Laura Gouveia
 Computer Science (Master)
IST Instituto Superior Tecnico - MEIC, Portugal
2019/12/02 - 2020/10/30 Blockchain technology for the construction industry
Supervisor of Tiago Furtado Piques Martins Mota
ISCTE-Instituto Universitário de Lisboa, Portugal
2019/12/09 - 2019/12/09 Open Source Face Recognition API
Co-supervisor of Diogo Neto Coxinho Mourisco da Conceição
ISCTE-Instituto Universitário de Lisboa, Portugal
2017/11/02 - 2018/12/18 Mixed reality application to support building maintenance
Co-supervisor of Hugo João Leitão Silva
ISCTE-Instituto Universitário de Lisboa, Portugal
2017/11/02 - 2018/12/06 Deep neural networks for image quality: a comparison study for identification photos
Co-supervisor of José Miguel Costa Ruivo
ISCTE-Instituto Universitário de Lisboa, Portugal

Event organisation

Event name
Type of event (Role) 		Institution / Organization
2019/06/22 - 2019/06/26 ACM/IEEE 2019 International Symposium on Computer Architecture (2019/06/22)
Conference (President of the Organising Committee)
2017/02/04 - 2017/02/08 International Symposium on Code Generationand Optimization (CGO) (2017/02/04)
2012/02/25 - 2012/02/29 18th International Symposium on High Performance Computer Architecture, 2012 (2012/02/25)
2007/09/27 - 2007/09/29 2007 IEEE International Symposium on Workload Characterization (2007/09/27)

Association member

Society Organization name Role
1991/01/01 - Current Senior Member IEEE

Course / Discipline taught

Academic session Degree Subject (Type) Institution / Organization
2018/02 - 2018/07 Development of Web Applications Open Source Software (Curso de mestrado (conclusão do curso de especialização)) ISCTE-Instituto Universitário de Lisboa, Portugal
2017/09 - 2018/01 Open Source Operating System Open Source Software (Curso de mestrado (conclusão do curso de especialização)) ISCTE-Instituto Universitário de Lisboa, Portugal
Distinctions

Other distinction

2024 IEEE Senior Life Member
2006 IEEE Senior Member