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Brunno Alves Abreu received a five-year engineering degree in Computer Engineering and the M.Sc. degree in Microelectronics from the Federal University of Rio Grande do Sul, Porto Alegre, Brazil, in 2017. He is currently a Ph.D. candidate at the Federal University of Rio Grande do Sul, Porto Alegre, Brazil. His research interests are low-power VLSI architectures, digital video compression, approximate computing and machine learning.
Identification

Personal identification

Full name
Brunno Alves de Abreu

Citation names

  • Abreu, Brunno

Author identifiers

Ciência ID
DF19-AF7B-87A3
ORCID iD
0000-0002-0467-0461

Knowledge fields

  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Electrical and Electronic Engineering

Languages

Language Speaking Reading Writing Listening Peer-review
Portuguese (Mother tongue)
English Proficiency (C2) Proficiency (C2) Proficiency (C2) Proficiency (C2) Proficiency (C2)
Spanish; Castilian Intermediate (B1) Upper intermediate (B2) Elementary (A2) Intermediate (B1) Intermediate (B1)
Education
Degree Classification
2019/08/01 - 2023/08/01
Ongoing
 Microeletronics Engineering (Doktor (PhD))
Universidade Federal do Rio Grande do Sul, Brazil
2018/03/23 - 2019/05/10
Concluded
 Microelectronics Engineering (Master)
Universidade Federal do Rio Grande do Sul, Brazil
"Exploring Partial Distortion Elimination Techniques in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation" (THESIS/DISSERTATION)
2018/03/22
Concluded
 Computer Engineering (Bachelor)
Universidade Federal do Rio Grande do Sul, Brazil
 9.55 (A)
Affiliation

Science

Category
Host institution 		Employer
2022/02/15 - Current Visiting Researcher (Research) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2016/03/01 - 2022/02/14 Researcher (Research) Universidade Federal do Rio Grande do Sul, Brazil
Outputs

Publications

Book chapter
  1. Diniz, Claudio M.; Abreu, Brunno; Grellert, Mateus; Sampaio, Felipe Martin; Palomino, Daniel; Livi Ramos, Fábio Luis; Zatt, Bruno; Bampi, Sergio. "Joint algorithm-architecture design of video coding modules". In VLSI Architectures for Future Video Coding, 41-77. Institution of Engineering and Technology, 2019.
    10.1049/pbcs053e_ch2
  2. Paim, Guilherme; Soares, Leonardo B.; Rocha, Leandro M.; Abreu, Brunno; Santana, Gustavo M.; Diniz, Claudio M.; Costa, Eduardo; Bampi, Sergio. "Low-power circuit design techniques for high-resolution video coding". In VLSI Architectures for Future Video Coding, 149-190. Institution of Engineering and Technology, 2019.
    10.1049/pbcs053e_ch5
Conference paper
  1. Wuerdig, Rodrigo; Sartori, Marcos; Abreu, Brunno; Bampi, Sergio; Calazans, Ney. "Mitigating Asynchronous QDI Drawbacks on Mac Operators with Approximate Multipliers". Paper presented in IEEE International Symposium on Circuits and Systems (ISCAS), Austin, 2022.
  2. Costa, Patricia; Pereira, Pedro; Abreu, Brunno; Paim, Guilherme; Costa, Eduardo; Bampi, Sergio. "Improved Approximate Multipliers for Single-Precision Floating-Point Hardware Design". Paper presented in 13th Latin American Symposium on Circuits and Systems, Santiago, 2022.
    Accepted
  3. Abreu, Brunno; Paim, Guilherme; Castro-Godínez, Jorge; Grellert, Mateus; Bampi, Sergio. "On the Netlist Gate-level Pruning for Tree-based Machine Learning Accelerators". Paper presented in 13th Latin American Symposium on Circuits and Systems, Santiago, 2022.
  4. Dick, Joao; Abreu, Brunno; Grellert, Mateus; Bampi, Sergio. "Quality and Complexity Assessment of Learning-Based Image Compression Solutions". Paper presented in IEEE International Conference on Image Processing (ICIP), Anchorage, 2021.
    10.1109/icip42928.2021.9506136
  5. Berndt, Augusto; Campos, Isac S.; Lima, Bryan; Grellert, Mateus; Carvalho, Jonata T.; Meinhardt, Cristina; Abreu, Brunno. "Accuracy and Size Trade-off of a Cartesian Genetic Programming Flow for Logic Optimization". Paper presented in 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, Campinas, 2021.
    10.1109/sbcci53441.2021.9529968
  6. Rai, Shubham; Neto, Walter Lau; Miyasaka, Yukio; Zhang, Xinpei; Yu, Mingfei; Yi, Qingyang; Fujita, Masahiro; et al. "Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization". Paper presented in Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, 2021.
    10.23919/date51398.2021.9473972
  7. Abreu, Brunno; Berndt, Augusto; Campos, Isac S.; Meinhardt, Cristina; Carvalho, Jonata T.; Grellert, Mateus; Bampi, Sergio. "Fast Logic Optimization Using Decision Trees". Paper presented in IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, 2021.
    10.1109/iscas51556.2021.9401664
  8. Abreu, Brunno; Grellert, Mateus; Bampi, Sergio. "VLSI Design of Tree-Based Inference for Low-Power Learning Applications". Paper presented in IEEE International Symposium on Circuits and Systems (ISCAS), Seville, 2020.
    10.1109/iscas45731.2020.9180704
  9. Abreu, Brunno; Grellert, Mateus; Paim, Guilherme; Fontanari, Thomas; Rocha, Leandro M. G.; Costa, Eduardo; Bampi, Sergio. "Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation". Paper presented in 17th IEEE International New Circuits and Systems Conference (NEWCAS), Munich, 2020.
    10.1109/newcas44328.2019.8961299
  10. Ferreira, Rafael S.; Paim, Guilherme; Abreu, Brunno; Diniz, Claudio M.; Costa, Eduardo; Bampi, Sergio. "HEVC Interpolation Filter Architecture Using Hybrid Encoding Arithmetic Operators". Paper presented in IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS), Dallas, 2019.
    10.1109/mwscas.2019.8885370
  11. Abreu, Brunno; Santana, Gustavo; Grellert, Mateus; Paim, Guilherme; Rocha, Leandro; Costa, Eduardo; Bampi, Sergio. "Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation". Paper presented in 31st Symposium on Integrated Circuits and Systems Design (SBCCI), Bento Gonçalves, 2018.
    10.1109/sbcci.2018.8533241
  12. Sequeira, Luis F.; Santana, Gustavo M.; Paim, Guilherme; Rocha, Leandro M. G.; Abreu, Brunno; Costa, Eduardo; Bampi, Sergio. "Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors". Paper presented in 16th IEEE International New Circuits and Systems Conference (NEWCAS), Montreal, 2018.
    10.1109/newcas.2018.8585470
  13. Rocha, Leandro M. G.; Paim, Guilherme; Santana, Gustavo M.; Abreu, Brunno; Ferreira, Rafael; Costa, Eduardo; Bampi, Sergio. "Physical implementation of an ASIC-oriented SRAM-based viterbi decoder". Paper presented in IEEE International Conference on Electronics, Circuits and Systems (ICECS), Batume, 2017.
    10.1109/icecs.2017.8292077
  14. Abreu, Brunno; Paim, Guilherme; Grellert, Mateus; Silveira, Bianca; Diniz, Claudio; Costa, Eduardo; Bampi, Sergio. "Exploiting absolute arithmetic for power-efficient sum of absolute differences". Paper presented in 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Batumi, 2017.
    10.1109/icecs.2017.8292062
  15. Silveira, Bianca; Abreu, Brunno; Paim, Guilherme; Grellert, Mateus; Ferreira, Rafael; Diniz, Claudio; Costa, Eduardo; Bampi, Sergio. "Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding". Paper presented in 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Batumi, 2017.
    10.1109/icecs.2017.8292076
Journal article
  1. Abreu, Brunno; Grellert, Mateus; Bampi, Sergio. "A framework for designing power-efficient inference accelerators in tree-based learning applications". Engineering Applications of Artificial Intelligence 109 (2022): 104638. http://dx.doi.org/10.1016/j.engappai.2021.104638.
    10.1016/j.engappai.2021.104638
  2. Paim, Guilherme; Amrouch, Hussam; Rocha, Leandro M. G.; Abreu, Brunno; Costa, Eduardo; Bampi, Sergio; Henkel, Jorg. "A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers". IEEE Transactions on Computers 71 2 (2022): 349-363. http://dx.doi.org/10.1109/tc.2021.3050978.
    10.1109/tc.2021.3050978
  3. Guilherme Paim; Hussam Amrouch; Leandro M. G. Rocha; Brunno Abreu; Eduardo Antonio Cesar da Costa; Sergio Bampi; Jorg Henkel. "A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers". IEEE Transactions on Computers (2022): https://doi.org/10.1109/TC.2021.3050978.
    10.1109/TC.2021.3050978
  4. Paim, Guilherme; Santana, Gustavo M.; Abreu, Brunno; Rocha, Leandro M. G.; Grellert, Mateus; Costa, Eduardo; Bampi, Sergio. "Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding". Journal of Real-Time Image Processing 17 5 (2020): 1735-1754. http://dx.doi.org/10.1007/s11554-019-00939-x.
    10.1007/s11554-019-00939-x
  5. Silveira, Bianca; Paim, Guilherme; Abreu, Brunno; Grellert, Mateus; Diniz, Claudio Machado; Costa, Eduardo; Bampi, Sergio. "Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design". IEEE Transactions on Circuits and Systems I: Regular Papers 64 12 (2017): 3126-3137. http://dx.doi.org/10.1109/tcsi.2017.2728802.
    Published • 10.1109/tcsi.2017.2728802
Activities

Oral presentation

Presentation title Event name
Host (Event location)
2022/03/02 On the Netlist Gate-level Pruning for Tree-based Machine Learning Accelerators 13th Latin American Symposium on Circuits and Systems
(Santiago, Chile)
2021/04/26 Exploring Decision Trees for Power-Aware Learning Applications 36th South Symposium on Microelectronics
(Porto Alegre, Brazil)
2020/11/10 Exploring Tree-Based Inference Engines for Low-Power Learning Applications IEEE CASS Rio Grande do Sul Workshop
Universidade Federal do Rio Grande do Sul (Porto Alegre, Brazil)
2020/07/22 Exploring Tree-Based Architectures for Power-Aware Learning Applications DAC Young Student Fellow Program
2019/05/07 Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation 3rd IEEE Seasonal School on Digital Processing of Visual Signals and Applications
2019/04/22 Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation 34th South Symposium on Microelectronics

Event participation

Activity description
Type of event 		Event name
Institution / Organization
2018/05/02 - 2018/05/05 Apresentação do artigo "Exploiting Absolute Arithmetic for Power-Efficient Sum of Absolute Differences"
Symposium
 33º Simpósio Sul de Microeletrônica
Universidade Federal do Paraná, Brazil
2017/10/16 - 2017/10/20 Apresentação do projeto de Iniciação Científica "Análise de Configurações de Memória Cache para o Algoritmo Hexagon Search para Codificação de Vídeo no Padrão HEVC".
Other
 XXIX Salão de Iniciação Científica UFRGS
Universidade Federal do Rio Grande do Sul, Brazil
2017/10/18 - 2017/10/19 Apresentação de pôster "Exploiting Cache Memory Configurations for Real-Time HEVC Hexagon Search Algorithm".
Workshop
 IEEE CASS Rio Grande do Sul Workshop
Universidade Federal do Rio Grande do Sul, Brazil
2016/09/12 - 2016/09/16 Apresentação do projeto de Iniciação Científica "Arquitetura do Test Zone Search para Codificação de Vídeo no Padrão HEVC".
Other
 XXVIII Salão de Iniciação Científica UFRGS
Universidade Federal do Rio Grande do Sul, Brazil
2016/05/11 - 2016/05/14 Apresentação do artigo "Test Zone Search Architecture for High-Definition Quality HEVC Encoding".
Symposium
 31st South Symposium on Microelectronics
Universidade Federal do Rio Grande do Sul, Brazil
2015/10/22 - 2015/10/23 Apresentação do pôster "High Throughput SAD Architecture for Quality HEVC Encoding".
Workshop
 5th IEEE CASS Rio Grande do Sul Workshop
Universidade Federal do Rio Grande do Sul, Brazil
2015/10/19 - 2015/10/23 Apresentação do projeto de Iniciação Científica "High Throughput SAD Architecture for Quality HEVC Encoding".
Other
 XXVII Salão de Iniciação Científica UFRGS
Universidade Federal do Rio Grande do Sul, Brazil
2015/05/05 - 2015/05/08 Apresentação do artigo "High Throughput SAD Architecture for Quality HEVC Encoding".
Symposium
 30th South Symposium on Microelectronics
Universidade Federal de Santa Maria, Brazil
Distinctions

Award

2021 Best Paper Award
2021 Best Paper Undergrad Award
2020 2nd Best Poster Award
2018 Aluno Destaque
Universidade Federal do Rio Grande do Sul, Brazil
2015 Best Poster Award - Undergraduate Students Track
Universidade Federal do Rio Grande do Sul, Brazil