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Filipe Azevedo has received his MSc. degree in Information Systems and Computer Engineering from Instituto Superior Técnico - University of Lisbon (IST-UL), Portugal, in 2020, with an M.Sc. thesis entitled “Evaluating value-wise poison values for the LLVM compiler”, where he achieved a grade of 18 out of 20. His master's training consolidated a strong foundation in machine learning, algorithms and programming, establishing the basis for a research career at applied artificial intelligence (AI). After some years in industry, in 2024 he returned to the academia to pursue his PhD. degree in Electrical and Computer Engineering from the same institution (IST-UL), on the topic of analog integrated circuit (IC) design automation assisted by state-of-the-art AI techniques, merging his solid background on software development with a complex real-world engineering application. Additionally, he is currently a researcher affiliated with Instituto de Telecomunicações, incorporating the Integrated Circuits Group (ICG-Lx). Since starting his Ph.D., he has been involved in 11 scientific publications, including 6 international conference articles. From these he would like to highlight a paper at the renowned Design Automation Conference (DAC) 2025 (rank A in CORE/EDA rankings), the flagship conference on electronic design automation, where he acted as a first author and major developer. Additionally, from the 3 journal articles that he has been involved, one of them, as first author and major developed, has been recently published in the high-impact factor (7.5) Expert Systems with Applications journal (Q1 in Scimago Journal Ranking in the AI, Computer Science Applications, and also, Engineering). Finally, he has taken a decisive role in two full books already published by Springer, which addressed groundbreaking AI applications towards analog IC design automation, in collaboration with other colleagues from IST-UL. During this period, he has also co-supervised two M.Sc. students, all of them achieving scientific publications from the outcome of their Master’s works, and, has been involved as vowel member on the jury of three other M.Sc. thesis of students from the Shanghai University (China). So far, he has been engaged in two on-going scientific projects with national and international institutes and/companies, namely, GENERALISE project (funded by Sony Advanced Visual Sensing AG, Switzerland), and ACTON (funded by Fundação para a Ciência e a Tecnologia). These projects reflect a successful engagement with industry, reinforcing his capacity to translate research into technological innovation. Additionally, the candidate has delivered 4 oral presentations at major international conferences (including DAC and the International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design) and has provided a talk to B.Sc. students of IST-UL, covering the challenges of automating microelectronics design with sophisticated AI tools. Filipe Azevedo has been highly driven towards knowledge sharing with research Institutes and Universities around the globe, actively collaborating with colleagues from the Technical University of Munich (Germany), Gebze Technical University (Turkey) and Shanghai University (China), all of them with published or currently submitted scientific papers.
Identificação

Identificação pessoal

Nome completo
Filipe Azevedo

Nomes de citação

  • Azevedo, Filipe
  • Parrado de Azevedo, Filipe

Identificadores de autor

Ciência ID
7B11-1614-A9B6

Endereços de correio eletrónico

  • filipepazevedo@gmail.com (Profissional)

Idiomas

Idioma Conversação Leitura Escrita Compreensão Peer-review
Português (Idioma materno)
Inglês Utilizador proficiente (C1) Utilizador proficiente (C2) Utilizador proficiente (C1) Utilizador proficiente (C2) Utilizador proficiente (C1)
Japonês Utilizador elementar (A2) Utilizador elementar (A2) Utilizador elementar (A2) Utilizador elementar (A2)
Formação
Grau Classificação
2024 - 2029
Em curso
Engenharia Electrotécnica e de Computadores (Doutoramento)
Especialização em Electronic Design Automation
Universidade de Lisboa Instituto Superior Técnico, Portugal

Instituto de Telecomunicações Lisboa, Portugal
"Generative AI Solutions for Analog Integrated Circuit Design" (TESE/DISSERTAÇÃO)
2017/09 - 2020/04
Concluído
Engenharia Informática e de Computadores (Mestrado)
Especialização em "Information and Language Processing Technology" and "Algorithms and Programming"
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Evaluating Value-Wise Poison Values for the LLVM Compiler" (TESE/DISSERTAÇÃO)
16
2014/09 - 2017/07
Concluído
Engenharia Informática e de Computadores (Licenciatura)
Universidade de Lisboa Instituto Superior Técnico, Portugal
16
Percurso profissional

Ciência

Categoria Profissional
Instituição de acolhimento
Empregador
2024/01/08 - Atual Investigador (Investigação) Instituto de Telecomunicações Lisboa, Portugal
Universidade de Lisboa Instituto Superior Técnico, Portugal

Outras Carreiras

Categoria Profissional
Instituição de acolhimento
Empregador
2021/01 - 2024/01 Consultor de Informática (Categorias e Funções Especificas) Deloitte Portugal, Portugal
Projetos

Projeto

Designação Financiadores
2024/01 - Atual Generative AI for Analog Chip Design
IT/SONY_AVGS
Instituto de Telecomunicações Lisboa, Portugal
Sony Advanced Visual Sensing AG
Em curso
2025/02/01 - 2026/07/31 Acelerando as Futuras Implementações de 5G/6G com Circuitos Integrados de Ondas Milimétricas Gerados por Visão Computacional Profunda
2023.11981.PEX
Bolseiro de Doutoramento
Instituto de Telecomunicações Lisboa, Portugal
Fundação para a Ciência e a Tecnologia
Em curso
Produções

Publicações

Artigo em conferência
  1. Paiva, Pedro; Azevedo, Filipe; Martins, Ricardo. "PVT-Inclusive mmWave IC Sizing Optimizations Boosted by ANN-based Performance Regressors and Transfer Learning". Trabalho apresentado em International Conference on Electronics, Circuits and Systems (ICECS), Marrakesh, 2025.
    Publicado • 10.1109/icecs66544.2025.11270700
  2. Azevedo, Filipe; Leibl, Markus; Martins, Ricardo; Graeb, Helmut. "Inverse Analog IC Sizing and Exploration through Diffusion Models and Structural Knowledge". Trabalho apresentado em International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD), Istanbul, 2025.
    Publicado • 10.1109/smacd65553.2025.11092111
  3. Costa, José; Azevedo, Filipe; Martins, Ricardo. "A Comparative Study on the Incorporation of PVT Corner Conditions within Reinforcement Learning-based Analog IC Sizing Approaches". Trabalho apresentado em International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Istanbul, 2025.
    Publicado • 10.1109/smacd65553.2025.11092187
  4. Azevedo, Filipe; Lourenço, Nuno; Martins, Ricardo. "Late Breaking Results: Encoder-Decoder Generative Diffusion Transformer Towards Push-Button Analog IC Sizing". Trabalho apresentado em Design Automation Conference (DAC), 2025.
    Publicado • 10.1109/dac63849.2025.11133224
  5. Eid, Pedro; Azevedo, Filipe; Martins, Ricardo; Lourenço, Nuno. "Solving the Inverse Problem of Analog Integrated Circuit Sizing with Diffusion Models". Trabalho apresentado em International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Volos, 2024.
    Publicado • 10.1109/smacd61181.2024.10745460
  6. Peneda, Diogo; Azevedo, Filipe; Lourenço, Nuno; Horta, Nuno; Martins, Ricardo. "Effective Routing Probability Maps via Convolutional Neural Networks for Analog IC Layout Automation". Trabalho apresentado em International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Volos, 2024.
    Publicado • 10.1109/smacd61181.2024.10745385
Artigo em revista
  1. Miguel Moura Ramos; Tomás Almeida; Vareta, Daniel; Azevedo, Filipe; Agrawal, Sweta; Patrick Fernandes; Martins, André F. T.. "Fine-Grained Reward Optimization for Machine Translation using Error Severity Mappings". Transactions of the Association for Computational Linguistics (TACL) (2026):
    Aceite para publicação
  2. de Azevedo, Filipe Parrado; Correia Lourenço, Nuno Calado; Ferreira Martins, Ricardo Miguel. "Comprehensive application of denoising diffusion probabilistic models towards the automation of analog integrated circuit sizing". Expert Systems with Applications 290 (2025): 128414. https://doi.org/10.1016/j.eswa.2025.128414.
    Publicado • 10.1016/j.eswa.2025.128414
  3. Eid, Pedro; Azevedo, Filipe; Lourenço, Nuno; Martins, Ricardo. "Using Denoising Diffusion Probabilistic Models to solve the inverse sizing problem of analog Integrated Circuits". AEU - International Journal of Electronics and Communications 195 (2025): 155767. https://doi.org/10.1016/j.aeue.2025.155767.
    Publicado • 10.1016/j.aeue.2025.155767
Livro
  1. Pedro Paiva; Mota, Jose; Azevedo, Filipe; Martins, Ricardo. Analog Integrated Circuit Design under PVT Conditions. Springer Nature Switzerland. 2026.
    Publicado
  2. H. M. Eid, Pedro; P. Azevedo, Filipe; C. C. Lourenço, Nuno; M. F. Martins, Ricardo. Efficient Analog Integrated Circuit Sizing with GenAI. Springer Nature Switzerland. 2025.
    Publicado • 10.1007/978-3-031-87105-4
Tese / Dissertação
  1. "Evaluating Value-Wise Poison Values for the LLVM Compiler". Mestrado, Universidade de Lisboa Instituto Superior Técnico, 2020. https://scholar.tecnico.ulisboa.pt/records/efPzAn6yUTToSsm5Xq4DSLGPct99Ka3cfTBm.
Atividades

Orientação

Título / Tema
Papel desempenhado
Curso (Tipo)
Instituição / Organização
2024 - 2025 Agents that Design Circuits: Reinforcement Learning Approach to Analog Integrated Circuit Design Automation
Coorientador
Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2024 - 2025 Speeding-Up PVT-Inclusive Analog/RF IC Sizing Optimizations With Artificial Neural Network based Performance Regressors and Transfer Learning
Coorientador
Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal

Júri de grau académico

Tema
Tipo de participação
Nome do candidato (Tipo de grau)
Instituição / Organização
2025/12/23 Using Variational Autoencoders to Address the Inverse Sizing Design Problem of Analog Integrated Circuits
Vogal
Liu Han (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2025/12/23 Design of Robust Electronic Circuits with Reinforcement Learning
Vogal
Yue Zhao (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2025/12/23 A Study of Different VAE–MLP-based Architectures for Post-Layout Performance Prediction of Analog Integrated Circuits
Vogal
Jiwang Zhou (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal

Arbitragem científica em conferência

Nome da conferência Local da conferência
2025 - 2025 International Conference on Computer-Aided Design (ICCAD) Munich
2025 - 2025 International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD) Istanbul
2024 - 2025 Design, Automation & Test in Europe (DATE) Lyon
Distinções

Outra distinção

2020 Diploma de Mérito Académico
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 Diploma de Mérito Académico
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016 Diploma de Mérito Académico
Universidade de Lisboa Instituto Superior Técnico, Portugal