???global.info.a_carregar???
Identificação

Identificação pessoal

Nome completo
Ricardo Miguel Ferreira Martins

Nomes de citação

  • Martins, Ricardo
  • R. Martins
  • R. M. F. Martins
  • Ricardo Martins

Identificadores de autor

Ciência ID
681C-0A3C-E8C2
ORCID iD
0000-0002-8251-1415
Google Scholar ID
https://scholar.google.pt/citations?hl=pt-PT&user=BQQtw4MAAAAJ
Scopus Author Id
55963115200

Websites

Domínios de atuação

  • Ciências da Engenharia e Tecnologias - Engenharia Eletrotécnica, Eletrónica e Informática

Idiomas

Idioma Conversação Leitura Escrita Compreensão Peer-review
Português Utilizador proficiente (C1) Utilizador proficiente (C1) Utilizador proficiente (C1) Utilizador proficiente (C1)
Inglês Utilizador proficiente (C1) Utilizador proficiente (C1) Utilizador proficiente (C1) Utilizador proficiente (C1)
Formação
Grau Classificação
2015/07
Concluído
 Engenharia Electrotécnica e de Computadores (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Placement, Routing and Parasitic Extraction Techniques applied to Analog IC Design Automation" (TESE/DISSERTAÇÃO)
 Pass with Distinction and Honour
2012/05
Concluído
 Engenharia Electrotécnica e de Computadores (Mestrado integrado)
Especialização em Electrónica, Telecomunicações
Universidade de Lisboa Instituto Superior Técnico, Portugal
"LAYGEN II - Automatic Layout Generation of Analog ICs based on Template Descriptions and Evolutionary Computation" (TESE/DISSERTAÇÃO)
 17
2011/06
Concluído
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Licenciatura)
Universidade de Lisboa Instituto Superior Técnico, Portugal
Percurso profissional

Ciência

Categoria Profissional
Instituição de acolhimento 		Empregador
2019/01 - 2022/12 Investigador Contratado (Investigação) Instituto de Telecomunicações, Portugal
Instituto de Telecomunicações, Portugal
2017/04 - 2018/12 Pós-doutorado (Investigação) Fundação para a Ciência e a Tecnologia, Portugal
Instituto de Telecomunicações, Portugal
2015/08 - 2017/03 Pós-doutorado (Investigação) Instituto de Telecomunicações, Portugal
Instituto de Telecomunicações, Portugal
2013/01 - 2015/07 Investigador (Investigação) Fundação para a Ciência e a Tecnologia, Portugal
Instituto de Telecomunicações, Portugal
2011/12 - 2012/12 Investigador (Investigação) Instituto de Telecomunicações, Portugal
Instituto de Telecomunicações, Portugal

Docência no Ensino Superior

Categoria Profissional
Instituição de acolhimento 		Empregador
2022/12 - Atual Professor Auxiliar (Docente Universitário) Universidade de Lisboa Instituto Superior Técnico, Portugal
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/02 - 2019/07 Professor Auxiliar Convidado (Docente Universitário) Universidade de Lisboa Instituto Superior Técnico, Portugal
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016/02 - 2016/07 Assistente Convidado (Docente Universitário) Universidade de Lisboa Instituto Superior Técnico, Portugal
Universidade de Lisboa Instituto Superior Técnico, Portugal
2012/09 - 2013/02 Assistente Convidado (Docente Universitário) Universidade de Lisboa Instituto Superior Técnico, Portugal
Universidade de Lisboa Instituto Superior Técnico, Portugal
Projetos

Projeto

Designação Financiadores
2020/02 - 2022/12 LAY(RF)^2 - Ready-to-Fabricate RF and mmWave Integrated Circuit Layouts
UIDB/50008/2020
Investigador responsável
Instituto de Telecomunicações, Portugal
 Instituto de Telecomunicações
Em curso
2020/01 - 2022/12 PROMISE - PROgrammable MIxed Signal Electronics
EU/H2020/870358
Investigador
Instituto de Telecomunicações, Portugal
 European Commission
Em curso
2020/05 - 2022/04 HAICAS - Hierarchical Analog IC Automatic Synthesis
UIDB/EEA/50008/2020
Investigador
Instituto de Telecomunicações, Portugal
 Instituto de Telecomunicações
Em curso
2013/10 - 2021/11 AIDA-C - Analog IC Optimizer
TAS / S01001
Investigador
Instituto de Telecomunicações, Portugal
 Thales Alenia Space
Em curso
2016/07 - 2018/06 RAPID - RF IC Design Automation
UID/EEA/50008/2013
Investigador
Instituto de Telecomunicações, Portugal
 Instituto de Telecomunicações
Concluído
2013/04 - 2016/03 DISRUPTIVE - A Paradigm shift in the design of analog and mixed-signal nanoelectronic circuits and systems
EXCL/EEI-ELC/0261/2012
Investigador
Instituto de Telecomunicações, Portugal
 Fundação para a Ciência e a Tecnologia
Concluído
2014/03 - 2016/02 OPERA - Layout-Aware Analog IC Design Automation
PEst-OE/EEI/LA0008/2013
Investigador
Instituto de Telecomunicações
Concluído
2011/10 - 2013/12 AIDA - Automated P-Cell Generation based on Multi-Objective Optimization and Pareto Optimal Front Circuit Level Characterization
IT/LA / P01112
Investigador
Instituto de Telecomunicações, Portugal
 Instituto de Telecomunicações
Concluído
Produções

Publicações

Artigo em conferência
  1. Pedro Vaz; António Gusmão; Prof. Doutor Nuno Cavaco Gomes Horta; Lourenço, Nuno; Martins, Ricardo. "Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator based on ANNs". Trabalho apresentado em IEEE International Symposium on Circuits and Systems (ISCAS), Austin, 2022.
    Aceite para publicação
  2. Luís Mendes; Caldinhas Vaz, João; Fábio Passos; Lourenço, Nuno; Martins, Ricardo. "Automatic Design of High-Gain 26.5-to-29.5-GHz Transformer-Less Low-Noise Amplifier 1.86-to-8.87-mW Variants in 65-nm CMOS". Trabalho apresentado em IEEE International Symposium on Circuits and Systems (ISCAS), Austin, 2022.
    Aceite para publicação
  3. António Gusmão; Nuno Horta; Nuno Lourenco; Martins, Ricardo. "Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement". Trabalho apresentado em Design Automation Conference (DAC) 2021, San Francisco, 2021.
    Submetido
  4. Martins, Ricardo; António Gusmão; António Canelas; Nuno Lourenco; Nuno Horta. "An Essay on the Next Generation of Performance-driven Analog/RF IC EDA Tools: The Role of Simulation-based Layout Optimization". Trabalho apresentado em International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design 2021, Erfurt, 2021.
    Submetido
  5. Rafael Vieira; Martins, Ricardo; Nuno Horta; Nuno Lourenco; Ricardo Póvoa. "A Sub-1µA Low-Power Low-Noise Amplifier with Tunable Gain and Bandwidth for EMG and EOG Biopotential Signals". Trabalho apresentado em 16th Conference on PhD Research in Microelectronics and Electronics, Erfurt, 2021.
    Submetido
  6. António Gusmão; António Canelas; Nuno Horta; Nuno Lourenco; Martins, Ricardo. "A Deep Learning Toolbox for Analog Integrated Circuit Placement". Trabalho apresentado em International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design 2021, Erfurt, 2021.
    Submetido
  7. Gusmao, Antonio; Passos, Fabio; Povoa, Ricardo; Horta, Nuno; Lourenco, Nuno; Martins, Ricardo. "Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender". Trabalho apresentado em IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Sevilha, 2020.
    10.1109/iscas45731.2020.9181148
  8. Martins, Ricardo. "Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing". 2019.
    10.1109/SMACD.2019.8795282
  9. Martins, Ricardo. "A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers". 2019.
    10.1109/SMACD.2019.8795248
  10. Martins, Ricardo. "On the exploration of design tradeoffs in analog IC placement with layout-dependent effects". 2019.
    10.1109/SMACD.2019.8795297
  11. Martins, Ricardo. "Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm". 2019.
    10.1109/SMACD.2019.8795240
  12. Martins, Ricardo. "Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization". 2019.
    10.1109/SMACD.2019.8795220
  13. Martins, Ricardo. "Artificial Neural Networks as an Alternative for Automatic Analog IC Placement". 2019.
    10.1109/SMACD.2019.8795267
  14. Martins, Ricardo. "A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications". 2018.
    10.1109/SMACD.2018.8434917
  15. Martins, Ricardo. "Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications". 2018.
    10.1109/SMACD.2018.8434853
  16. Martins, Ricardo. "Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs". 2018.
    10.1109/SMACD.2018.8434887
  17. Martins, Ricardo. "Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel". 2018.
    10.23919/DATE.2018.8342092
  18. Martins, Ricardo. "On the Exploration of Promising Analog IC Designs via Artificial Neural Networks". 2018.
    10.1109/SMACD.2018.8434896
  19. Martins, Ricardo. "Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks". 2017.
    10.1109/SMACD.2017.7981577
  20. Martins, Ricardo. "New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization". 2017.
    10.1109/SMACD.2017.7981582
  21. Martins, Ricardo. "A dynamic voltage-combiners biased OTA for low-power and high-speed SC circuits". 2017.
    10.1109/PRIME.2017.7974122
  22. Martins, Ricardo. "Systematic design of a voltage controlled oscillator using a layout-aware approach". 2017.
    10.1109/SMACD.2017.7981580
  23. Martins, Ricardo. "Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing". 2017.
    10.23919/DATE.2017.7927171
  24. Martins, Ricardo. "Automated Analog IC Design Constraints Generation for a Layout-Aware Sizing Approach". 2016.
    10.1109/SMACD.2016.7520740
  25. Martins, Ricardo. "Yield Optimization using K-Means Clustering Algorithm to reduce Monte Carlo Simulations". 2016.
    10.1109/SMACD.2016.7520729
  26. Martins, Ricardo. "On-the-fly Exploration of Placement Templates for Analog IC Layout-aware Sizing Methodologies". 2016.
    10.1109/SMACD.2016.7520731
  27. Neves, D.; Martins, R.; Lourenço, N.; Horta, N.. "Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approach". 2016.
  28. Martins, R.; Lourenco, N.; Horta, N.; Guerreiro, N.; Santos, M.. "Embedding Fault List Compression Techniques in a Design Automation Framework for Analog And Mixed-signal Structural Testing". 2016.
    10.1109/DCIS.2015.7388584
  29. Lourenco, N.; Martins, R.; Horta, N.. "Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction". 2015.
  30. Martins, R.; Lourenco, N.; Canelas, A.; Horta, N.. "Extraction and application of wiring symmetry rules to route analog multiport terminals". 2015.
    10.1109/ISCAS.2015.7169054
  31. Cardoso, B.; Martins, R.; Lourenco, N.; Horta, N.. "AIDA-PEx: Accurate parasitic extraction for layout-aware analog integrated circuit sizing". 2015.
    10.1109/PRIME.2015.7251351
  32. Martins, R.; Povoa, R.; Lourenco, N.; Horta, N.. "Exploring design tradeoffs in analog IC placement with current-flow & current-density considerations". 2015.
    10.1109/SMACD.2015.7301697
  33. Martins, R.; Lourenco, N.; Canelas, A.; Povoa, R.; Horta, N.. "AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation". 2015.
    10.1109/SMACD.2015.7301703
  34. Martins, Ricardo. "Analog IC placement using absolute coordinates and a hierarchical combination of Pareto optimal fronts". 2015.
    10.1109/PRIME.2015.7251334
  35. Martins, R.; Lourenco, N.; Canelas, A.; Horta, N.. "Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures". 2014.
    10.7873/DATE2014.023
  36. Povoa, R.; Lourenco, R.; Lourenco, N.; Canelas, A.; Martins, R.; Horta, N.. "LC-VCO automatic synthesis using multi-objective evolutionary techniques". 2014.
    10.1109/ISCAS.2014.6865123
  37. Rocha, F.; Martins, R.; Lourenço, N.; Horta, N.. "Enhancing a layout-aware synthesis methodology for analog ics by embedding statistical knowledge into the evolutionary optimization kernel". Trabalho apresentado em Proceedings of the Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS-2013), 2013.
  38. Rocha, F.; Lourenco, N.; Povoa, R.; Martins, R.; Horta, N.. "A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis". 2013.
    10.1109/CEC.2013.6557906
  39. Martins, R.; Lourenco, N.; Canelas, A.; Horta, N.. "Multi-port multi-terminal analog router based on an evolutionary optimization kernel". 2013.
    10.1109/CEC.2013.6557907
  40. Martins, R.; Lourenço, N.; Horta, N.. "LAYGEN II: Automatic analog ICs layout generator based on a template approach". 2012.
    10.1145/2330163.2330319
  41. Martins, R.; Lourenço, N.; Horta, N.. "Multi-objective multi-constraint routing of analog ICs using a modified NSGA-II approach". 2012.
    10.1109/SMACD.2012.6339418
  42. Martins, R.; Lourenço, N.; Rodrigues, S.; Guilherme, J.; Horta, N.. "AIDA: Automated analog IC design flow from circuit level to layout". 2012.
    10.1109/SMACD.2012.6339409
Artigo em revista
  1. António Gusmão; Ricardo Filipe Sereno Póvoa; Nuno Horta; Nuno Lourenço; Ricardo Martins. "DeepPlacer: A custom integrated OpAmp placement tool using deep models". Applied Soft Computing Journal 115 1 (2022): 108188-108188. http://www.it.pt/Publications/PaperJournal/31984.
    10.1016/j.asoc.2021.108188
  2. António Gusmão; Horta, Nuno Cavaco Gomes; Lourenço, Nuno; Martins, Ricardo. "Scalable and Order Invariant Analog Integrated Circuit Placement with Attention-based Graph-to-Sequence Deep Models". Expert Systems with Applications (2022):
    Em revisão
  3. Afacan, Engin; Lourenço, Nuno; Martins, Ricardo; Dündar, Günhan. "Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test". Integration 77 (2021): 113-130. http://dx.doi.org/10.1016/j.vlsi.2020.11.006.
    10.1016/j.vlsi.2020.11.006
  4. Martins, Ricardo; Lourenço, Nuno; Póvoa, Ricardo; Horta, Nuno. "Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing". Engineering Applications of Artificial Intelligence 98 (2021): 104102. http://dx.doi.org/10.1016/j.engappai.2020.104102.
    10.1016/j.engappai.2020.104102
  5. Luis Mendes; Joao Caldinhas Vaz; Fabio Passos; Nuno Lourenco; Ricardo Martins. "In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization". IEEE Access 9 (2021): 70353-70368. https://doi.org/10.1109/ACCESS.2021.3078240.
    10.1109/ACCESS.2021.3078240
  6. Antonio Canelas; Fabio Passos; Nuno Lourenco; Ricardo Martins; Elisenda Roca; Rafael Castro-Lopez; Nuno Horta; Francisco V. Fernandez. "Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs". IEEE Access 9 (2021): 124152-124164. https://doi.org/10.1109/ACCESS.2021.3110758.
    10.1109/ACCESS.2021.3110758
  7. Ricardo Martins; Nuno Lourenco; Nuno Horta; Shenke Zhong; Jun Yin; Pui In Mak; Rui P. Martins. "Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools". IEEE Transactions on Circuits and Systems I: Regular Papers 67 11 (2020): 3965-3977. https://doi.org/10.1109/TCSI.2020.3009857.
    Publicado • 10.1109/TCSI.2020.3009857
  8. Póvoa, Ricardo; Canelas, António; Martins, Ricardo; Horta, Nuno; Lourenço, Nuno; Goes, João. "A new family of CMOS inverter-based OTAs for biomedical and healthcare applications". Integration 71 (2020): 38-48. http://dx.doi.org/10.1016/j.vlsi.2019.12.004.
    10.1016/j.vlsi.2019.12.004
  9. Povoa, Ricardo; Lourenco, Nuno; Martins, Ricardo; Canelas, Antonio; Horta, Nuno; Goes, Joao; Ricardo Povoa; et al. "A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications". IEEE Transactions on Circuits and Systems II: Express Briefs 67 2 (2020): 230-234. http://dx.doi.org/10.1109/tcsii.2019.2913083.
    10.1109/tcsii.2019.2913083
  10. Póvoa, Ricardo; Arya, Richa; Canelas, António; Passos, Fábio; Martins, Ricardo; Lourenço, Nuno; Horta, Nuno. "Sub-µW Tow-Thomas based biquad filter with improved gain for biomedical applications". Microelectronics Journal 95 (2020): 104675. http://dx.doi.org/10.1016/j.mejo.2019.104675.
    10.1016/j.mejo.2019.104675
  11. Canelas, Antonio; Povoa, Ricardo; Martins, Ricardo; Lourenco, Nuno; Guilherme, Jorge; Carvalho, Joao Paulo; Horta, Nuno; et al. "FUZYE: A Fuzzy c-Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39 1 (2020): 1-13. http://dx.doi.org/10.1109/tcad.2018.2883978.
    10.1109/tcad.2018.2883978
  12. Fabio Passos; Elisenda Roca; Ricardo Martins; Nuno Lourenco; Saiyd Ahyoune; Javier Sieiro; Rafael Castro-Lopez; et al. "Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology". IEEE Access 8 (2020): 51601-51609. https://doi.org/10.1109/ACCESS.2020.2980211.
    10.1109/ACCESS.2020.2980211
  13. Martins, Ricardo; Lourenco, Nuno; Horta, Nuno; Yin, Jun; Mak, Pui-In; Martins, Rui P.; Ricardo Martins; et al. "Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 1 (2019): 69-82. http://dx.doi.org/10.1109/tvlsi.2018.2872410.
    10.1109/tvlsi.2018.2872410
  14. Fábio Passos; Ricardo Martins; Nuno Lourenço; Elisenda Roca; Ricardo Filipe Sereno Póvoa; António Canelas; Rafael Castro-López; Nuno Horta; Francisco Fernández. "Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology". Integration, The VLSI Journal 63 n/a (2018): 351-361. http://www.it.pt/Publications/PaperJournal/27961.
    10.1016/j.vlsi.2018.02.005
  15. Ricardo Martins; Nuno Lourenço; Fábio Passos; Ricardo Filipe Sereno Póvoa; António Canelas; Elisenda Roca; Rafael Castro-López; et al. "Two-Step RF IC Block Synthesis with Pre-Optimized Inductors and Full Layout Generation In-the-loop". IEEE Transactions on Computer-Aided Design Early Acce Early Acce (2018): Early Access-Early Access. http://www.it.pt/Publications/PaperJournal/27960.
    10.1109/TCAD.2018.2834394
  16. Ricardo Filipe Sereno Póvoa; Nuno Lourenço; Ricardo Martins; António Canelas; Nuno Horta; João Goes. "Single Stage OTA biased by Voltage-Combiners with Enhanced Performance using Current Starving". IEEE Transactions on Circuits and Systems II: Express Briefs 1 1 (2017): 1-5. http://www.it.pt/Publications/PaperJournal/23723.
    10.1109/TCSII.2017.2777533
  17. Ricardo Martins; Nuno Lourenço; António Canelas; Nuno Horta. "Stochastic-based placement template generator for analog IC layout-aware synthesis". Integration, The VLSI Journal 58 n/a (2017): 485-495. http://www.it.pt/Publications/PaperJournal/22639.
    10.1016/j.vlsi.2017.02.012
  18. Ricardo Filipe Sereno Póvoa; Nuno Lourenço; Ricardo Martins; António Canelas; Nuno Horta; João Goes. "Single-Stage Amplifier biased by Voltage-Combiners with Gain and Energy-Efficiency Enhancement". IEEE Transactions on Circuits and Systems II: Express Briefs PP 99 (2017): 1-1. http://www.it.pt/Publications/PaperJournal/22648.
    10.1109/TCSII.2017.2686586
  19. Martins, Ricardo. "Current-flow & Current-Density-aware Multi-Objective Optimization of Analog IC Placement". Integration, the VLSI Journal (2016):
    10.1016/j.vlsi.2016.05.008
  20. Lourenço, N.; Martins, R.; Canelas, A.; Póvoa, R.; Horta, N.. "AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation". Integration, the VLSI Journal (2016): http://www.scopus.com/inward/record.url?eid=2-s2.0-84966648845&partnerID=MN8TOARS.
    10.1016/j.vlsi.2016.04.009
  21. Martins, R.; Lourenço, N.; Horta, N.. "Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates". Expert Systems with Applications 42 23 (2015): 9137-9151. http://www.scopus.com/inward/record.url?eid=2-s2.0-84940827353&partnerID=MN8TOARS.
    10.1016/j.eswa.2015.08.020
  22. Martins, R.; Lourenço, N.; Canelas, A.; Horta, N.. "Electromigration-aware analog Router with multilayer multiport terminal structures". Integration, the VLSI Journal 47 4 (2014): 532-547. http://www.scopus.com/inward/record.url?eid=2-s2.0-84903315430&partnerID=MN8TOARS.
    10.1016/j.vlsi.2014.02.003
  23. Martins, R.; Lourenço, N.; Horta, N.. "Routing analog ICs using a multi-objective multi-constraint evolutionary approach". Analog Integrated Circuits and Signal Processing 78 1 (2014): 123-135. http://www.scopus.com/inward/record.url?eid=2-s2.0-84892669296&partnerID=MN8TOARS.
    10.1007/s10470-013-0088-9
  24. Lourenço, N.; Canelas, A.; Póvoa, R.; Martins, R.; Horta, N.. "Floorplan-aware analog IC sizing and optimization based on topological constraints". Integration, the VLSI Journal (2014): http://www.scopus.com/inward/record.url?eid=2-s2.0-84906072112&partnerID=MN8TOARS.
    10.1016/j.vlsi.2014.07.002
  25. Martins, R.; Lourenço, N.; Horta, N.. "LAYGEN II-automatic layout generation of analog integrated circuits". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32 11 (2013): 1641-1654. http://www.scopus.com/inward/record.url?eid=2-s2.0-84886665180&partnerID=MN8TOARS.
    10.1109/TCAD.2013.2269050
Capítulo de livro
  1. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "State-of-the-Art in Analog Integrated Circuit Placement". 2020.
    10.1007/978-3-030-50061-0_3
  2. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "Results". 2020.
    10.1007/978-3-030-50061-0_5
  3. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "Introduction". 2020.
    10.1007/978-3-030-50061-0_1
  4. Martins, Ricardo. "Synthesis of LC-oscillators using rival multi- objective multi-constraint optimization kernels". 1-27. 2014.
    10.4018/978-1-4666-6627-6.ch001
  5. Martins, Ricardo. "Enhancing an automatic analog IC design flow by using a technology- independent module generator". 102-133. 2014.
    10.4018/978-1-4666-6627-6.ch005
  6. Lourenço, Nuno; Martins, Ricardo; Barros, Manuel; Horta, Nuno. "Analog Circuit Design Based on Robust POFs Using an Enhanced MOEA with SVM Models". In Analog/RF and Mixed-Signal Circuit Systematic Design, 149-167. Springer Berlin Heidelberg, 2013.
    10.1007/978-3-642-36329-0_7
Edição de número de revista
  1. Martins, Ricardo. "Special Issue on Selected Papers from PRIME and SMACD 2019". Integration, the VLSI (2020):
    Publicado • Editor
Livro
  1. Rosa, João P. S.; Guerra, Daniel J. D.; Horta, Nuno C. G.; Martins, Ricardo M. F.; Lourenço, Nuno C. C.. Using Artificial Neural Networks for Analog Integrated Circuit Design Automation. Springer International Publishing. 2020.
    10.1007/978-3-030-35743-6
  2. Gusmão, António; Horta, Nuno; Lourenço, Nuno; Martins, Ricardo. Analog IC Placement Generation via Neural Networks from Unlabeled Data. Springer International Publishing. 2020.
    10.1007/978-3-030-50061-0
  3. Lourenço, Nuno; Martins, Ricardo; Horta, Nuno; Martins, Ricardo. Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects. Springer International Publishing. 2017.
    10.1007/978-3-319-42037-0
  4. Martins, Ricardo. Analog Integrated Circuit Design Automation – Placement, Routing and Parasitic Extraction Techniques. 2016.
    10.1007/978-3-319-34060-9
  5. Electronic Design Automation of Analog ICs combining Gradient Models with Multi-Objective Evolutionary Algorithms. 2014.
  6. Martins, Ricardo M. F.; Lourenço, Nuno C. C.; Horta, Nuno C. G.. Generating Analog IC Layouts with LAYGEN II. Springer Berlin Heidelberg. 2013.
    10.1007/978-3-642-33146-6
Poster em conferência
  1. Martins, Ricardo; N. C. C. Lourenço; N. Horta; J. Yin; P. Mak; R. P. Martins. "Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications". Trabalho apresentado em Design Automation Conference (DAC) Work-in-Progress, 2018.
Prefácio / Posfácio
  1. Martins, Ricardo. "2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)". Estados Unidos: IEEE. 2019.
    Publicado
Tese / Dissertação
  1. Martins, Ricardo. "Placement, Routing and Parasitic Extraction Techniques applied to Analog IC Design Automation". Doutoramento, Universidade de Lisboa Instituto Superior Técnico, 2015.
  2. Martins, Ricardo. "LAYGEN II - Automatic Layout Generation of Analog ICs based on Template Descriptions and Evolutionary Computation". Mestrado, Universidade de Lisboa Instituto Superior Técnico, 2012.

Outros

Outra produção
  1. TSMC65nm Integrated Circuit Prototype. Europractice TSMC 65nm CMOS LP MS/RF run 9170. 2022.
  2. Managing editor of the Proceedings of the International Conference on SMACD 2019. Proceedings of the International Conference on SMACD 2019, published on IEEE Xplore DOI: 10.1109/SMACD46049.2019. 2019. Martins, Ricardo. https://ieeexplore.ieee.org/servlet/opac?punumber=8786808.
Atividades

Apresentação oral de trabalho

Título da apresentação Nome do evento
Anfitrião (Local do evento)
2020/10 Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender IEEE International Symposium on Circuits and Systems (ISCAS)
(Seville, Espanha)
2020/08 Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools IEEE International Symposium on Integrated Circuits and Systems (ISICAS)
(Paris, França)
2018/07 Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (Prague, República Checa)
2017/06 Layout-Aware Challenges and a Solution for the Automatic Synthesis of Radio-Frequency IC Blocks International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (Giardini Naxos, Itália)
2016/06 On-the-fly Exploration of Placement Templates for Analog IC Layout-aware Sizing Methodologies International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (Lisbon, Portugal)
2015/11 Embedding Fault List Compression Techniques in a Design Automation Framework for Analog and Mixed-Signal Structural Testing Conference on Design of Circuits and Integrated Systems (DCIS)
Conference on Design of Circuits and Integrated Systems (DCIS) (Estoril, Portugal)
2015/09 AIDA: Robust Layout-aware Synthesis of Analog ICs including Sizing and Layout Generation Design Automation Competition
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (Istanbul, Turquia)
2015/09 Exploring Design Tradeoffs in Analog IC Placement with Current-flow & Current-density Considerations International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (Istanbul, Turquia)
2015/06 Analog IC Placement using Absolute Coordinates and a Hierarchical Combination of Pareto Optimal Fronts IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME)
IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME) (Glasgow, Reino Unido)
2015/06 AIDA-PEx: Accurate Parasitic Extraction for Layout-Aware Analog Integrated Circuit Sizing IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME)
IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME) (Glasgow, Reino Unido)
2015/05 Extraction and Application of Wiring Symmetry Rules to Route Analog Multiport Terminals IEEE International Symposium on Circuits and Systems (IEEE ISCAS)
IEEE International Symposium on Circuits and Systems (IEEE ISCAS) (Lisbon, Portugal)
2014/03 Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures Design, Automation & Test in Europe (DATE) Conference
Design, Automation & Test in Europe (DATE) Conference (Dresden, Alemanha)
2012/09 Multi-Objective Multi-Constraint Routing of Analog ICs using a Modified NSGA-II Approach International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (Seville, Espanha)
2012/07 Human-competitive Analog IC Layout Generation “Humies Competition” (Human-Competitive Results Produced by Genetic and Evolutionary Computation)
Genetic and Evolutionary Computation Conference (Philadelphia, Estados Unidos)
2012/07 LAYGEN II - Automatic Analog ICs Layout Generator based on a Template Approach Genetic and Evolutionary Computation Conference
Genetic and Evolutionary Computation Conference (Philadelphia, Estados Unidos)

Orientação

Título / Tema
Papel desempenhado 		Curso (Tipo)
Instituição / Organização
2020/04 - 2023/12 Deep Learning Techniques for End-to-end Deep Nanometer Analog and Radio Frequency Integrated Circuit Design Automation
Orientador
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2021 - 2022 Improving Sampling Efficiency of Multi-Net Multi-Terminal Analog Integrated Circuit Routing with Machine Learning
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020/09 - 2021/10 ANN-based Floorplan Recommender for Large Analog IC Building Blocks with Multiple Topological Constraints Coverage
Orientador
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020/09 - 2021/10 Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator using Deep ANNs
Orientador
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020/09 - 2021/10 Accelerating Voltage-Controlled Oscillator Sizing Optimizations with a Convergence Classifier & Frequency Guess Predictor
Orientador
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2019/02 - 2019/10 Semi-Supervised Artificial Neural Networks towards Push-Button Analog IC Placement
Orientador
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/02 - 2018/10 EDA to the cloud: a case study to increase both effectiveness and user experience of EDA tools
Coorientador
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/02 - 2018/10 On the Exploration of Automatic Analog Integrated Circuit Placement using Neural Networks
Orientador
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/09 - 2018/06 Using Artificial Neural Networks to Size Analog Integrated Circuits
Coorientador
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/02 - 2017/11 Enhanced Analog and RF IC Sizing Methodology using PCA and NSGA-II Optimization Kernel
Coorientador
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2014/09 - 2015/05 AIDA-PEx: Parasitic Extraction on Layout-Aware Analog Integrated Circuit Sizing
Coorientador
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal

Organização de evento

Nome do evento
Tipo de evento (Tipo de participação) 		Instituição / Organização
2022 - Atual SMACD 2022 Technical Program Chair (2022/06)
Conferência (Coorganizador)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design 2022, Itália
2021 - Atual SMACD 2021 Technical Program Chair (2020 - 2021/07)
Conferência (Coorganizador)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2021, Alemanha
2023/01 - 2023/07 SMACD 2023 Technical Program Chair (2023/07/03 - 2023/07/05)
Conferência (Coorganizador)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD) 2023, Portugal
2016 - 2022 SMACD Technical Program Committee (2016 - 2021)
Conferência (Membro da Comissão Científica)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2016, 2017, 2018, 2019, 2021, Alemanha
2016 - 2022 PRIME Technical Program Committee (2016 - 2021)
Conferência (Membro da Comissão Científica)
 IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME) 2016, 2017, 2018, 2019, 2021, Alemanha
2019 - 2019 SMACD 2019 General Chair (2019/07 - 2019/07)
Conferência (Presidente da Comissão Organizadora)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2019 Committee, Suiça
2019 - 2019 IEEE ICECS 2019 Awards Chair (2019/11 - 2019/11)
Conferência (Membro da Comissão Organizadora)
 IEEE International Conference on Electronics Circuits and Systems (ICECS) 2019, Itália
2018/07 - 2018/07 SMACD 2018 Special Session Organizer (2018/07 - 2018/07)
Conferência (Membro da Comissão Organizadora)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2018 Committee, República Checa
2017 - 2017 SMACD 2017 Publication Chair (2017/06 - 2017/06)
Conferência (Membro da Comissão Organizadora)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2017 Committee, Itália
2017 - 2017 NGCAS 2017 Competition Chair "Best YP industrial and societal application" (2017/09 - 2017/09)
Conferência (Membro da Comissão Organizadora)
 New Generation of Circuits and Systems Conference (NGCAS) 2017, Itália
2016 - 2016 SMACD 2016 Competition Chair "Improve design automation for integrated circuits and systems" (2016/06 - 2016/06)
Conferência (Membro da Comissão Organizadora)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2016 Committee, Portugal
2016 - 2016 SMACD 2016 Publication Chair (2016/06 - 2016/06)
Conferência (Membro da Comissão Organizadora)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2016 Committee, Portugal
2016 - 2016 PRIME 2016 Publication Chair (2016/06 - 2016/06)
Conferência (Membro da Comissão Organizadora)
 Conference on PhD Research in Microelectronics and Electronics (PRIME) 2016, Portugal
2015 - 2015 ISCAS 2015 Local Organizing Committee Member (2015/05 - 2015/05)
Simpósio (Outra)
 IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Portugal
2014 - 2014 23rd AACD Local Organizing Committee Member (2014/04 - 2014/04)
Oficina (workshop) (Outra)
 23rd Workshop on Advances in Analog Circuit Design , Portugal

Júri de grau académico

Tema
Tipo de participação 		Nome do candidato (Tipo de grau)
Instituição / Organização
2021/11 Study of Variability Phenomena on CMOS Technologies for its Mitigation and Exploitation
Arguente principal
 Pablo Sarazá Canflanca (Doutoramento)
Universidad de Sevilla, Espanha
2019/10 Semi-Supervised Artificial Neural Networks towards Push-Button Analog IC Placement
Orientador
 António Gusmão (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2019/01 Energy-Efficient Computing: Adaptive Structures and Data Management
Arguente
 Nuno Neves (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/10 On the Exploration of Automatic Analog Integrated Circuit Placement using Neural Networks
Orientador
 Daniel Guerra (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/05 AIDA-PEx: Parasitic Extraction on Layout-Aware Analog Integrated Circuit Sizing
Orientador
 Bruno Cardoso (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal

Arbitragem científica em conferência

Nome da conferência Local da conferência
2016 - 2021 Conference on PhD Research in Microelectronics and Electronics Several Editions
2016 - 2021 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design Several Editions
2015 - 2021 IEEE International Symposium on Circuits and Systems Several Editions
2019 - 2019 IEEE International Conference on Electronics Circuits and Systems Genova, Italy
2018 - 2018 IEEE Computer Society Annual Symposium on VLSI Hong Kong, China
2017 - 2017 1st Conference on New Generation of Circuits and Systems Genova, Italy

Arbitragem científica em revista

Nome da revista (ISSN) Editora
2020 - 2021 Mathematical and Computational Applications Open Access Journal (2297-8747) MDPI
2020 - 2021 Electronics Open Access Journal (2079-9292) MDPI
2017 - 2021 IEEE Transactions on Circuits and Systems I: Regular Papers (1549-8328) IEEE
2016 - 2021 IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems (0278-0070) IEEE
2016 - 2021 Turkish Journal of Electrical Engineering & Computer Sciences (1300-0632) Tübitak
2016 - 2021 Applied Soft Computing (1568-4946) Elsevier
2015 - 2021 IET Computers & Digital Techniques Journal (0143-7062) IET Digital Library
2015 - 2021 Integration, the VLSI Journal (0167-9260) Elsevier

Curso / Disciplina lecionado

Disciplina Curso (Tipo) Instituição / Organização
2016 - 2019 Systems Programming Engenharia Electrotécnica e de Computadores (Mestrado integrado) Universidade de Lisboa Instituto Superior Técnico, Portugal
2015 - 2016 Computer Architecture Engenharia Electrotécnica e de Computadores (Mestrado integrado) Universidade de Lisboa Instituto Superior Técnico, Portugal
2012 - 2013 Digital Systems Engenharia Electrotécnica e de Computadores (Mestrado integrado) Universidade de Lisboa Instituto Superior Técnico, Portugal

Membro de comissão

Descrição da atividade
Tipo de participação 		Instituição / Organização
2019 - Atual SMACD 2021 Steering Committee
Membro
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2021, Alemanha
Distinções

Prémio

2019 SMACD 2019 Best Paper Award Runner-Up
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2019 Committee, Suiça
2019 Integration, the VLSI Journal 2019 Best Paper Award
Integration, the VLSI Journal, Elsevier, Países Baixos
2018 SMACD 2018 Best Paper Award
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2018 Committee, República Checa
2016 SMACD 2016 Best Paper Award
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2016 Committee, Portugal
2015 PRIME 2015 Silver Leaf Best Paper Award
IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME) 2015 Committee, Reino Unido
2015 1st Ranked on SMACD "Design Automation Competition" (1000USD prize)
2014 ISCAS 2014 Student Best Paper Award Runner-Up
IEEE International Symposium on Circuits and Systems (ISCAS) 2015 Committee, Austrália

Outra distinção

2020 IST Outstanding Teaching Award
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018 IST Outstanding Teaching Award
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 SMACD 2017 Best Paper Award Nominee
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2017 Committee, Itália
2014 IST Outstanding Teaching Award
Universidade de Lisboa Instituto Superior Técnico, Portugal
2012 Finalist of the GECCO "Humies Competition"
Genetic and Evolutionary Computation Conference (GECCO) 2012 Committee, Estados Unidos
2012 Honorable Mention from SMACD "Design Automation Competition"
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2012 Committee, Espanha