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Identification

Personal identification

Full name
Ricardo Miguel Ferreira Martins

Citation names

  • Martins, Ricardo
  • R. Martins
  • R. M. F. Martins
  • Ricardo Martins

Author identifiers

Ciência ID
681C-0A3C-E8C2
ORCID iD
0000-0002-8251-1415
Google Scholar ID
https://scholar.google.pt/citations?hl=pt-PT&user=BQQtw4MAAAAJ
Scopus Author Id
55963115200

Websites

Knowledge fields

  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics

Languages

Language Speaking Reading Writing Listening Peer-review
Portuguese (Mother tongue)
English Advanced (C1) Advanced (C1) Advanced (C1) Advanced (C1)
Spanish; Castilian Intermediate (B1) Intermediate (B1) Intermediate (B1) Intermediate (B1) Intermediate (B1)
Education
Degree Classification
2015/07
Concluded
 Engenharia Electrotécnica e de Computadores (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Placement, Routing and Parasitic Extraction Techniques applied to Analog IC Design Automation" (THESIS/DISSERTATION)
 Pass with Distinction and Honour
2012/05
Concluded
 Engenharia Electrotécnica e de Computadores (Mestrado integrado)
Major in Electrónica, Telecomunicações
Universidade de Lisboa Instituto Superior Técnico, Portugal
"LAYGEN II - Automatic Layout Generation of Analog ICs based on Template Descriptions and Evolutionary Computation" (THESIS/DISSERTATION)
 17
2011/06
Concluded
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Licenciatura)
Universidade de Lisboa Instituto Superior Técnico, Portugal
Affiliation

Science

Category
Host institution 		Employer
2019/01 - 2022/12 Contracted Researcher (Research) Instituto de Telecomunicações, Portugal
Instituto de Telecomunicações, Portugal
2017/04 - 2018/12 Postdoc (Research) Fundação para a Ciência e a Tecnologia, Portugal
Instituto de Telecomunicações, Portugal
2015/08 - 2017/03 Postdoc (Research) Instituto de Telecomunicações, Portugal
Instituto de Telecomunicações, Portugal
2013/01 - 2015/07 Researcher (Research) Fundação para a Ciência e a Tecnologia, Portugal
Instituto de Telecomunicações, Portugal
2011/12 - 2012/12 Researcher (Research) Instituto de Telecomunicações, Portugal
Instituto de Telecomunicações, Portugal

Teaching in Higher Education

Category
Host institution 		Employer
2022/12 - Current Assistant Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/02 - 2019/07 Invited Assistant Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016/02 - 2016/07 Invited Assistant (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
Universidade de Lisboa Instituto Superior Técnico, Portugal
2012/09 - 2013/02 Invited Assistant (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
Universidade de Lisboa Instituto Superior Técnico, Portugal
Projects

Contract

Designation Funders
2025/02/01 - 2026/07/31 Acelerando as Futuras Implementações de 5G/6G com Circuitos Integrados de Ondas Milimétricas Gerados por Visão Computacional Profunda
2023.11981.PEX
10.54499/2023.11981.PEX
Instituto de Telecomunicações Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Ongoing
2023/05/01 - 2026/04/01 Generative AI for Analog Chip Design
IT/SONY_AVGS
Principal investigator
Instituto de Telecomunicações, Portugal
 Sony Advanced Visual Sensing AG
Ongoing
2021/01/01 - 2023/12/31 Institute of Telecommunications
LA/P/0109/2020
10.54499/LA/P/0109/2020
UID/EEA/50008/2019
Instituto de Telecomunicações Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2020/02 - 2023/12 LAY(RF)^2 - Ready-to-Fabricate RF and mmWave Integrated Circuit Layouts
UIDB/50008/2020
Principal investigator
Instituto de Telecomunicações, Portugal
 Instituto de Telecomunicações
Concluded
2020/01 - 2022/12 PROMISE - PROgrammable MIxed Signal Electronics
EU/H2020/870358
Researcher
Instituto de Telecomunicações, Portugal
 European Commission
Concluded
2020/05 - 2022/04 HAICAS - Hierarchical Analog IC Automatic Synthesis
UIDB/EEA/50008/2020
Researcher
Instituto de Telecomunicações, Portugal
 Instituto de Telecomunicações
Ongoing
2020/02/01 - 2022/02/01 Ready-to-Fabricate RF and mmWave Integrated Circuit Layouts
n/d
Instituto de Telecomunicações Lisboa, Portugal
Ongoing
2013/10 - 2021/11 AIDA-C - Analog IC Optimizer
TAS / S01001
Researcher
Instituto de Telecomunicações, Portugal
 Thales Alenia Space
Ongoing
2016/07 - 2018/06 RAPID - RF IC Design Automation
UID/EEA/50008/2013
Researcher
Instituto de Telecomunicações, Portugal
 Instituto de Telecomunicações
Concluded
2013/04 - 2016/03 DISRUPTIVE - A Paradigm shift in the design of analog and mixed-signal nanoelectronic circuits and systems
EXCL/EEI-ELC/0261/2012
Researcher
Instituto de Telecomunicações, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2014/03 - 2016/02 OPERA - Layout-Aware Analog IC Design Automation
PEst-OE/EEI/LA0008/2013
Researcher
Instituto de Telecomunicações
Concluded
2011/10 - 2013/12 AIDA - Automated P-Cell Generation based on Multi-Objective Optimization and Pareto Optimal Front Circuit Level Characterization
IT/LA / P01112
Researcher
Instituto de Telecomunicações, Portugal
 Instituto de Telecomunicações
Concluded
Outputs

Publications

Book
  1. Pedro Paiva; Mota, Jose; Azevedo, Filipe; Martins, Ricardo. Analog Integrated Circuit Design under PVT Conditions. Springer Nature Switzerland. 2026.
    In press
  2. Pedro H. M. Eid; Filipe P. Azevedo; Nuno C. C. Lourenço; Ricardo M. F. Martins. Efficient Analog Integrated Circuit Sizing with GenAI. 2025.
    10.1007/978-3-031-87105-4
  3. João Domingues; Pedro Vaz; António Gusmão; Prof. Doutor Nuno Cavaco Gomes Horta; Nuno Calado Correia Lourenço; Ricardo Miguel Ferreira Martins. Speeding-Up Radio-Frequency Integrated Circuit Sizing with Neural Networks. SpringerBriefs in Computational Intelligence, Springer. 2023.
    Published
  4. Rosa, João P. S.; Guerra, Daniel J. D.; Horta, Nuno C. G.; Martins, Ricardo M. F.; Lourenço, Nuno C. C.. Using Artificial Neural Networks for Analog Integrated Circuit Design Automation. Springer International Publishing. 2020.
    10.1007/978-3-030-35743-6
  5. Gusmão, António; Horta, Nuno; Lourenço, Nuno; Martins, Ricardo. Analog IC Placement Generation via Neural Networks from Unlabeled Data. Springer International Publishing. 2020.
    10.1007/978-3-030-50061-0
  6. Lourenço, Nuno; Martins, Ricardo; Horta, Nuno; Martins, Ricardo. Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects. Springer International Publishing. 2017.
    10.1007/978-3-319-42037-0
  7. Martins, Ricardo. Analog Integrated Circuit Design Automation – Placement, Routing and Parasitic Extraction Techniques. 2016.
    10.1007/978-3-319-34060-9
  8. Electronic Design Automation of Analog ICs combining Gradient Models with Multi-Objective Evolutionary Algorithms. 2014.
  9. Martins, Ricardo M. F.; Lourenço, Nuno C. C.; Horta, Nuno C. G.. Generating Analog IC Layouts with LAYGEN II. Springer Berlin Heidelberg. 2013.
    10.1007/978-3-642-33146-6
Book chapter
  1. Pedro H. M. Eid; Filipe P. Azevedo; Nuno C. C. Lourenço; Ricardo M. F. Martins. "Proposed Architectures". 2025.
    10.1007/978-3-031-87105-4_3
  2. Pedro H. M. Eid; Filipe P. Azevedo; Nuno C. C. Lourenço; Ricardo M. F. Martins. "Experimental Results". 2025.
    10.1007/978-3-031-87105-4_5
  3. Pedro H. M. Eid; Filipe P. Azevedo; Nuno C. C. Lourenço; Ricardo M. F. Martins. "Introduction". 2025.
    10.1007/978-3-031-87105-4_1
  4. Pedro H. M. Eid; Filipe P. Azevedo; Nuno C. C. Lourenço; Ricardo M. F. Martins. "Model Implementation and Optimization". 2025.
    10.1007/978-3-031-87105-4_4
  5. Pedro H. M. Eid; Filipe P. Azevedo; Nuno C. C. Lourenço; Ricardo M. F. Martins. "State-of-the-Art". 2025.
    10.1007/978-3-031-87105-4_2
  6. Pedro H. M. Eid; Filipe P. Azevedo; Nuno C. C. Lourenço; Ricardo M. F. Martins. "Conclusion and Future Works". 2025.
    10.1007/978-3-031-87105-4_6
  7. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "Artificial Neural Network Overview". 2020.
    10.1007/978-3-030-50061-0_2
  8. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "State-of-the-Art in Analog Integrated Circuit Placement". 2020.
    10.1007/978-3-030-50061-0_3
  9. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "ANN Models for Analog Placement Automation". 2020.
    10.1007/978-3-030-50061-0_4
  10. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "Introduction". 2020.
    10.1007/978-3-030-50061-0_1
  11. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "Conclusions and Future Work". 2020.
    10.1007/978-3-030-50061-0_6
  12. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "Results". 2020.
    10.1007/978-3-030-50061-0_5
  13. Martins, Ricardo. "Synthesis of LC-oscillators using rival multi- objective multi-constraint optimization kernels". 1-27. 2014.
    10.4018/978-1-4666-6627-6.ch001
  14. Martins, Ricardo. "Enhancing an automatic analog IC design flow by using a technology- independent module generator". 102-133. 2014.
    10.4018/978-1-4666-6627-6.ch005
  15. Lourenço, Nuno; Martins, Ricardo; Barros, Manuel; Horta, Nuno. "Analog Circuit Design Based on Robust POFs Using an Enhanced MOEA with SVM Models". In Analog/RF and Mixed-Signal Circuit Systematic Design, 149-167. Springer Berlin Heidelberg, 2013.
    10.1007/978-3-642-36329-0_7
Conference abstract
  1. Fábio Passos; Lourenço, Nuno; Luís Miguel Moreira Mendes; Martins, Ricardo; Caldinhas Vaz, João; Nuno Horta. "A 23.5-32.5GHz, 17dBm PSAT and 37.5%PAE Power Amplifier Fully Synthesized Using an Automated Design Methodology Aided by ML Passive Component Models". Paper presented in International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD), 2023.
    Accepted
Conference paper
  1. Paiva, Pedro; Azevedo, Filipe; Martins, Ricardo. "PVT-Inclusive mmWave IC Sizing Optimizations Boosted by ANN-based Performance Regressors and Transfer Learning". Paper presented in International Conference on Electronics, Circuits and Systems (ICECS), Marrakesh, 2025.
    Published • 10.1109/icecs66544.2025.11270700
  2. Azevedo, Filipe; Leibl, Markus; Martins, Ricardo; Graeb, Helmut. "Inverse Analog IC Sizing and Exploration through Diffusion Models and Structural Knowledge". Paper presented in International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD), Istanbul, 2025.
    Published • 10.1109/smacd65553.2025.11092111
  3. Costa, José; Azevedo, Filipe; Martins, Ricardo. "A Comparative Study on the Incorporation of PVT Corner Conditions within Reinforcement Learning-based Analog IC Sizing Approaches". Paper presented in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Istanbul, 2025.
    Published • 10.1109/smacd65553.2025.11092187
  4. Azevedo, Filipe; Lourenço, Nuno; Martins, Ricardo. "Late Breaking Results: Encoder-Decoder Generative Diffusion Transformer Towards Push-Button Analog IC Sizing". Paper presented in Design Automation Conference (DAC), 2025.
    Published • 10.1109/dac63849.2025.11133224
  5. Passos, Fábio; Martins, Ricardo; Lourenço, Nuno. "Low-Power 9.6-11GHz and 10.8-12GHz VCOs Designed for a 2.5/5GHz TRx using High-Q Inductors Synthesized with ML Techniques". 2024.
    10.1109/smacd61181.2024.10745382
  6. Martins, Ricardo; Gusmão, António; Vieira, Rafael; Passos, Fábio; Lourenço, Nuno; Horta, Nuno. "Ponderous: A Performance-driven Analog IC Placement Optimizer Leveraged by a ML Pipeline". 2024.
    10.1109/smacd61181.2024.10745469
  7. Eid, Pedro; Azevedo, Filipe; Martins, Ricardo; Lourenço, Nuno. "Solving the Inverse Problem of Analog Integrated Circuit Sizing with Diffusion Models". Paper presented in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Volos, 2024.
    Published • 10.1109/smacd61181.2024.10745460
  8. Peneda, Diogo; Azevedo, Filipe; Lourenço, Nuno; Horta, Nuno; Martins, Ricardo. "Effective Routing Probability Maps via Convolutional Neural Networks for Analog IC Layout Automation". Paper presented in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Volos, 2024.
    Published • 10.1109/smacd61181.2024.10745385
  9. Fábio Moreira de Passos; Lourenço, Nuno; Luís Mendes; Martins, Ricardo; Caldinhas Vaz, João; Nuno Horta. "A 23.5-32.5GHz, 17dBm PSAT and 37.5% PAE Power Amplifier Synthesized Using an Automated Design Methodology". Paper presented in International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD 2023), Funchal - Madeira, 2023.
  10. Santos, Carlos; Fernandes, Jorge; Santos, Marcelino; Martins, Ricardo. "Paving the Way for the Electronic Design Automation of Power Management Units". 2023.
    10.1109/smacd58065.2023.10192230
  11. Amaral, André; Gusmão, António; Vieira, Rafael; Martins, Ricardo; Horta, Nuno; Lourenço, Nuno. "An ANN-Based Approach to the Modelling and Simulation of Analogue Circuits". 2023.
    10.1109/smacd58065.2023.10192134
  12. Vieira, Rafael; Martins, Ricardo; Horta, Nuno; Lourenço, Nuno. "Design Space Exploration of Single-Stage OTAs towards an Ultra-Low-Power LNA for ECG Signals". 2023.
    10.1109/smacd58065.2023.10192218
  13. Passos, Fábio; Lourenço, Nuno; Mendes, Luís; Martins, Ricardo; Vaz, João; Horta, Nuno. "A 23.5–32.5GHz, 17dBm PSAT and 37.5% PAE Power Amplifier Synthesized Using an Automated Design Methodology". 2023.
    10.1109/smacd58065.2023.10192226
  14. Passos, F.; Lourenço, N.; Mendes, L.; Martins, R.; Vaz, J.; Horta, N.. "Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning Models". 2023.
    10.1145/3566097.3567879
  15. Vieira, Rafael; Passos, Fabio; Povoa, Ricardo; Martins, Ricardo; Horta, Nuno; Guilherme, Jorge; Lourenco, Nuno. "Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling". 2022.
    10.1109/smacd55068.2022.9816253
  16. Lourenco, Nuno; Passos, Fabio; Vieira, Rafael; Martins, Ricardo; Horta, Nuno; Guilherme, Jorge; Povoa, Ricardo. "Radiation-Hardened Bandgap Voltage and Current Reference for Space Applications with 2.38 ppm/°C Temperature Coefficient". 2022.
    10.1109/smacd55068.2022.9816300
  17. Fábio Passos; Lourenço, Nuno; Martins, Ricardo; Elisenda Roca; Rafael Castro-Lopez; Horta, Nuno Cavaco Gomes; Fernández, Francisco. "Machine Learning Approaches for Transformer Modeling". Paper presented in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Sardinia, 2022.
    Published
  18. João Domingues; António Gusmão; Horta, Nuno Cavaco Gomes; Lourenço, Nuno; Martins, Ricardo. "Accelerating Voltage-Controlled Oscillator Sizing Optimizations with ANN-based Convergence Classifiers and Frequency Guess Predictors". Paper presented in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Sardinia, 2022.
    Published
  19. Pedro Alves; António Gusmão; Nuno Horta; Lourenço, Nuno; Martins, Ricardo. "ANN-based Analog IC Floorplan Recommender with a Broader Topological Constraints Coverage". Paper presented in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Sardinia, 2022.
    Submitted
  20. Pedro Vaz; António Gusmão; Prof. Doutor Nuno Cavaco Gomes Horta; Lourenço, Nuno; Martins, Ricardo. "Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator based on ANNs". Paper presented in IEEE International Symposium on Circuits and Systems (ISCAS), Austin, 2022.
    Published
  21. Luís Mendes; Caldinhas Vaz, João; Fábio Passos; Lourenço, Nuno; Martins, Ricardo. "Automatic Design of High-Gain 26.5-to-29.5-GHz Transformer-Less Low-Noise Amplifier 1.86-to-8.87-mW Variants in 65-nm CMOS". Paper presented in IEEE International Symposium on Circuits and Systems (ISCAS), Austin, 2022.
    Accepted
  22. António Gusmão; Nuno Horta; Nuno Lourenco; Martins, Ricardo. "Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement". Paper presented in Design Automation Conference (DAC) 2021, San Francisco, 2021.
    Submitted
  23. Gusmão, António; Horta, Nuno; Lourenço, Nuno; Ricardo Martins. "Bringing Structure into Analog IC Placement with Relational Graph Convolutional Networks". Paper presented in International Conference On Synthesis, Modeling, Analysis And Simulation Methods And Applications To Circuit Design (SMACD), Erfurt, 2021.
    Accepted
  24. Martins, Ricardo; António Gusmão; António Canelas; Nuno Lourenco; Nuno Horta. "An Essay on the Next Generation of Performance-driven Analog/RF IC EDA Tools: The Role of Simulation-based Layout Optimization". Paper presented in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design 2021, Erfurt, 2021.
    Submitted
  25. Rafael Vieira; Martins, Ricardo; Nuno Horta; Nuno Lourenco; Ricardo Póvoa. "A Sub-1µA Low-Power Low-Noise Amplifier with Tunable Gain and Bandwidth for EMG and EOG Biopotential Signals". Paper presented in 16th Conference on PhD Research in Microelectronics and Electronics, Erfurt, 2021.
    Submitted
  26. António Gusmão; António Canelas; Nuno Horta; Nuno Lourenco; Martins, Ricardo. "A Deep Learning Toolbox for Analog Integrated Circuit Placement". Paper presented in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design 2021, Erfurt, 2021.
    Submitted
  27. L. Mendes; J. Vaz; F. Passos; Lourenço, Nuno; R. M. F. Martins. "Design Space Exploration of 26.5-to-29.5-GHz Low-Noise Amplifiers for Low-Power mmWave 5G Communications in 65-nm CMOS". Paper presented in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Erfurt, 2021.
    Submitted
  28. Gusmao, Antonio; Passos, Fabio; Povoa, Ricardo; Horta, Nuno; Lourenco, Nuno; Martins, Ricardo. "Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender". Paper presented in IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Sevilha, 2020.
    10.1109/iscas45731.2020.9181148
  29. Martins, Ricardo. "Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing". 2019.
    10.1109/SMACD.2019.8795282
  30. Martins, Ricardo. "A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers". 2019.
    10.1109/SMACD.2019.8795248
  31. Martins, Ricardo. "On the exploration of design tradeoffs in analog IC placement with layout-dependent effects". 2019.
    10.1109/SMACD.2019.8795297
  32. Martins, Ricardo. "Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm". 2019.
    10.1109/SMACD.2019.8795240
  33. Martins, Ricardo. "Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization". 2019.
    10.1109/SMACD.2019.8795220
  34. Martins, Ricardo. "Artificial Neural Networks as an Alternative for Automatic Analog IC Placement". 2019.
    10.1109/SMACD.2019.8795267
  35. Martins, Ricardo. "A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications". 2018.
    10.1109/SMACD.2018.8434917
  36. Martins, Ricardo. "Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications". 2018.
    10.1109/SMACD.2018.8434853
  37. Martins, Ricardo. "Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs". 2018.
    10.1109/SMACD.2018.8434887
  38. Martins, Ricardo. "Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel". 2018.
    10.23919/DATE.2018.8342092
  39. Martins, Ricardo. "On the Exploration of Promising Analog IC Designs via Artificial Neural Networks". 2018.
    10.1109/SMACD.2018.8434896
  40. Martins, Ricardo. "Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks". 2017.
    10.1109/SMACD.2017.7981577
  41. Martins, Ricardo. "New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization". 2017.
    10.1109/SMACD.2017.7981582
  42. Martins, Ricardo. "A dynamic voltage-combiners biased OTA for low-power and high-speed SC circuits". 2017.
    10.1109/PRIME.2017.7974122
  43. Martins, Ricardo. "Systematic design of a voltage controlled oscillator using a layout-aware approach". 2017.
    10.1109/SMACD.2017.7981580
  44. Martins, Ricardo. "Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing". 2017.
    10.23919/DATE.2017.7927171
  45. Martins, Ricardo. "Automated Analog IC Design Constraints Generation for a Layout-Aware Sizing Approach". 2016.
    10.1109/SMACD.2016.7520740
  46. Martins, Ricardo. "Yield Optimization using K-Means Clustering Algorithm to reduce Monte Carlo Simulations". 2016.
    10.1109/SMACD.2016.7520729
  47. Martins, Ricardo. "On-the-fly Exploration of Placement Templates for Analog IC Layout-aware Sizing Methodologies". 2016.
    10.1109/SMACD.2016.7520731
  48. Neves, D.; Martins, R.; Lourenço, N.; Horta, N.. "Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approach". 2016.
  49. Martins, R.; Lourenco, N.; Horta, N.; Guerreiro, N.; Santos, M.. "Embedding Fault List Compression Techniques in a Design Automation Framework for Analog And Mixed-signal Structural Testing". 2016.
    10.1109/DCIS.2015.7388584
  50. Lourenco, N.; Martins, R.; Horta, N.. "Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction". 2015.
  51. Martins, R.; Lourenco, N.; Canelas, A.; Horta, N.. "Extraction and application of wiring symmetry rules to route analog multiport terminals". 2015.
    10.1109/ISCAS.2015.7169054
  52. Cardoso, B.; Martins, R.; Lourenco, N.; Horta, N.. "AIDA-PEx: Accurate parasitic extraction for layout-aware analog integrated circuit sizing". 2015.
    10.1109/PRIME.2015.7251351
  53. Martins, R.; Povoa, R.; Lourenco, N.; Horta, N.. "Exploring design tradeoffs in analog IC placement with current-flow & current-density considerations". 2015.
    10.1109/SMACD.2015.7301697
  54. Martins, R.; Lourenco, N.; Canelas, A.; Povoa, R.; Horta, N.. "AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation". 2015.
    10.1109/SMACD.2015.7301703
  55. Martins, Ricardo. "Analog IC placement using absolute coordinates and a hierarchical combination of Pareto optimal fronts". 2015.
    10.1109/PRIME.2015.7251334
  56. Martins, R.; Lourenco, N.; Canelas, A.; Horta, N.. "Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures". 2014.
    10.7873/DATE2014.023
  57. Povoa, R.; Lourenco, R.; Lourenco, N.; Canelas, A.; Martins, R.; Horta, N.. "LC-VCO automatic synthesis using multi-objective evolutionary techniques". 2014.
    10.1109/ISCAS.2014.6865123
  58. Rocha, F.; Martins, R.; Lourenço, N.; Horta, N.. "Enhancing a layout-aware synthesis methodology for analog ics by embedding statistical knowledge into the evolutionary optimization kernel". Paper presented in Proceedings of the Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS-2013), 2013.
  59. Rocha, F.; Lourenco, N.; Povoa, R.; Martins, R.; Horta, N.. "A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis". 2013.
    10.1109/CEC.2013.6557906
  60. Martins, R.; Lourenco, N.; Canelas, A.; Horta, N.. "Multi-port multi-terminal analog router based on an evolutionary optimization kernel". 2013.
    10.1109/CEC.2013.6557907
  61. Martins, R.; Lourenço, N.; Horta, N.. "LAYGEN II: Automatic analog ICs layout generator based on a template approach". 2012.
    10.1145/2330163.2330319
  62. Martins, R.; Lourenço, N.; Horta, N.. "Multi-objective multi-constraint routing of analog ICs using a modified NSGA-II approach". 2012.
    10.1109/SMACD.2012.6339418
  63. Martins, R.; Lourenço, N.; Rodrigues, S.; Guilherme, J.; Horta, N.. "AIDA: Automated analog IC design flow from circuit level to layout". 2012.
    10.1109/SMACD.2012.6339409
Conference poster
  1. Martins, Ricardo; N. C. C. Lourenço; N. Horta; J. Yin; P. Mak; R. P. Martins. "Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications". Paper presented in Design Automation Conference (DAC) Work-in-Progress, 2018.
Journal article
  1. Ricardo M. F. Martins. "A Survey of Machine and Deep Learning Techniques in Analog Integrated Circuit Layout Synthesis". Microelectronics (2025): https://doi.org/10.3390/microelectronics1010002.
    10.3390/microelectronics1010002
  2. Eid, Pedro; Azevedo, Filipe; Lourenço, Nuno; Martins, Ricardo. "Using Denoising Diffusion Probabilistic Models to solve the inverse sizing problem of analog Integrated Circuits". AEU - International Journal of Electronics and Communications 195 (2025): 155767. https://doi.org/10.1016/j.aeue.2025.155767.
    Published • 10.1016/j.aeue.2025.155767
  3. Luís Mendes; Silva, João; Lourenço, Nuno; Vaz, João Caldinhas; Martins, Ricardo; Passos, Fábio. "Fully Automatically Synthesized mm-Wave Low-Noise Amplifiers for 5G/6G Applications". IEEE Transactions on Microwave Theory and Techniques (2025): 1-0. https://doi.org/10.1109/tmtt.2025.3537588.
    10.1109/tmtt.2025.3537588
  4. Luís Mendes; João Silva; Nuno Lourenço; João Caldinhas Vaz; Ricardo Martins; Fábio Passos. "Fully Automatically Synthesized mm-Wave Low-Noise Amplifiers for 5G/6G Applications". IEEE Transactions on Microwave Theory and Techniques (2025): https://doi.org/10.1109/TMTT.2025.3537588.
    10.1109/TMTT.2025.3537588
  5. Ricardo Martins. "Closing the Gap Between Electrical and Physical Design Steps with an Analog IC Placement Optimizer Enhanced with Machine-Learning-Based Post-Layout Performance Regressors". Electronics (2024): https://doi.org/10.3390/electronics13224360.
    10.3390/electronics13224360
  6. Rafael Vieira; Fabian Näf; Ricardo Martins; Nuno Horta; Nuno Lourenço; Ricardo Póvoa. "A Tunable Gain and Bandwidth Low-Noise Amplifier with 1.44 NEF for EMG and EOG Biopotential Signal". Electronics (2023): https://doi.org/10.3390/electronics12122592.
    10.3390/electronics12122592
  7. Fábio Passos; Nuno Lourenço; Elisenda Roca; Ricardo Martins; Rafael Castro-López; Nuno Horta; Francisco V. Fernández. "PACOSYT: A Passive Component Synthesis Tool Based on Machine Learning and Tailored Modeling Strategies Towards Optimal RF and mm-Wave Circuit Designs". IEEE Journal of Microwaves (2023): https://doi.org/10.1109/JMW.2023.3237260.
    10.1109/JMW.2023.3237260
  8. Ricardo M. F. Martins; Nuno C. C. Lourenço. "Analog Integrated Circuit Routing Techniques: An Extensive Review". IEEE Access (2023): https://doi.org/10.1109/ACCESS.2023.3265481.
    10.1109/ACCESS.2023.3265481
  9. Rafael Vieira; Fábio Passos; Ricardo Martins; Nuno Horta; Nuno Lourenço. "Behavioral Analysis of Noise and Bandwidth Specifications of Heartbeat Detection Circuits for Ultra Low Power Devices". IEEE Access (2023): https://doi.org/10.1109/ACCESS.2023.3255166.
    10.1109/ACCESS.2023.3255166
  10. António Gusmão; Pedro Alves; Nuno Horta; Nuno Lourenço; Ricardo Martins. "Differentiable Constraints’ Encoding for Gradient-Based Analog Integrated Circuit Placement Optimization". Electronics (2022): https://doi.org/10.3390/electronics12010110.
    10.3390/electronics12010110
  11. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "Scalable and order invariant analog integrated circuit placement with Attention-based Graph-to-Sequence deep models". Expert Systems with Applications 207 1 (2022): 117954-117954. http://www.it.pt/Publications/PaperJournal/33514.
    10.1016/j.eswa.2022.117954
  12. António Gusmão; Rafael Alexandre Ascenso Vieira; Nuno Horta; Nuno Lourenço; Ricardo Martins. "Exploiting a Deep Learning Toolbox for Human-Machine Feedback towards Analog Integrated Circuit Placement Automation". Electronics (Switzerland) 11 23 (2022): 1-1. http://www.it.pt/Publications/PaperJournal/33515.
    10.3390/electronics11233964
  13. António Gusmão; Ricardo Filipe Sereno Póvoa; Nuno Horta; Nuno Lourenço; Ricardo Martins. "DeepPlacer: A custom integrated OpAmp placement tool using deep models". Applied Soft Computing Journal 115 1 (2022): 108188-108188. http://www.it.pt/Publications/PaperJournal/31984.
    10.1016/j.asoc.2021.108188
  14. António Gusmão; Horta, Nuno Cavaco Gomes; Lourenço, Nuno; Martins, Ricardo. "Scalable and Order Invariant Analog Integrated Circuit Placement with Attention-based Graph-to-Sequence Deep Models". Expert Systems with Applications (2022):
    Under revision
  15. Afacan, Engin; Lourenço, Nuno; Martins, Ricardo; Dündar, Günhan. "Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test". Integration 77 (2021): 113-130. http://dx.doi.org/10.1016/j.vlsi.2020.11.006.
    10.1016/j.vlsi.2020.11.006
  16. Martins, Ricardo; Lourenço, Nuno; Póvoa, Ricardo; Horta, Nuno. "Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing". Engineering Applications of Artificial Intelligence 98 (2021): 104102. http://dx.doi.org/10.1016/j.engappai.2020.104102.
    10.1016/j.engappai.2020.104102
  17. Luis Mendes; Joao Caldinhas Vaz; Fabio Passos; Nuno Lourenco; Ricardo Martins. "In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization". IEEE Access 9 (2021): 70353-70368. https://doi.org/10.1109/ACCESS.2021.3078240.
    10.1109/ACCESS.2021.3078240
  18. Antonio Canelas; Fabio Passos; Nuno Lourenco; Ricardo Martins; Elisenda Roca; Rafael Castro-Lopez; Nuno Horta; Francisco V. Fernandez. "Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs". IEEE Access 9 (2021): 124152-124164. https://doi.org/10.1109/ACCESS.2021.3110758.
    10.1109/ACCESS.2021.3110758
  19. Gusmão, António; Póvoa, Ricardo; Martins, Ricardo; Horta, Nuno; Lourenço, Nuno. "DeepPlacer: A Custom Analog Integrated Circuit Placement Tool using Deep Models". Applied Soft Computing (2021):
    Under revision
  20. Ricardo Martins; Nuno Lourenco; Nuno Horta; Shenke Zhong; Jun Yin; Pui In Mak; Rui P. Martins. "Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools". IEEE Transactions on Circuits and Systems I: Regular Papers 67 11 (2020): 3965-3977. https://doi.org/10.1109/TCSI.2020.3009857.
    Published • 10.1109/TCSI.2020.3009857
  21. Póvoa, Ricardo; Canelas, António; Martins, Ricardo; Horta, Nuno; Lourenço, Nuno; Goes, João. "A new family of CMOS inverter-based OTAs for biomedical and healthcare applications". Integration 71 (2020): 38-48. http://dx.doi.org/10.1016/j.vlsi.2019.12.004.
    10.1016/j.vlsi.2019.12.004
  22. Povoa, Ricardo; Lourenco, Nuno; Martins, Ricardo; Canelas, Antonio; Horta, Nuno; Goes, Joao; Ricardo Povoa; et al. "A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications". IEEE Transactions on Circuits and Systems II: Express Briefs 67 2 (2020): 230-234. http://dx.doi.org/10.1109/tcsii.2019.2913083.
    10.1109/tcsii.2019.2913083
  23. Póvoa, Ricardo; Arya, Richa; Canelas, António; Passos, Fábio; Martins, Ricardo; Lourenço, Nuno; Horta, Nuno. "Sub-µW Tow-Thomas based biquad filter with improved gain for biomedical applications". Microelectronics Journal 95 (2020): 104675. http://dx.doi.org/10.1016/j.mejo.2019.104675.
    10.1016/j.mejo.2019.104675
  24. Canelas, Antonio; Povoa, Ricardo; Martins, Ricardo; Lourenco, Nuno; Guilherme, Jorge; Carvalho, Joao Paulo; Horta, Nuno; et al. "FUZYE: A Fuzzy c-Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39 1 (2020): 1-13. http://dx.doi.org/10.1109/tcad.2018.2883978.
    10.1109/tcad.2018.2883978
  25. Fabio Passos; Elisenda Roca; Ricardo Martins; Nuno Lourenco; Saiyd Ahyoune; Javier Sieiro; Rafael Castro-Lopez; et al. "Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology". IEEE Access 8 (2020): 51601-51609. https://doi.org/10.1109/ACCESS.2020.2980211.
    10.1109/ACCESS.2020.2980211
  26. Martins, Ricardo; Lourenco, Nuno; Horta, Nuno; Yin, Jun; Mak, Pui-In; Martins, Rui P.; Ricardo Martins; et al. "Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 1 (2019): 69-82. http://dx.doi.org/10.1109/tvlsi.2018.2872410.
    10.1109/tvlsi.2018.2872410
  27. Fábio Passos; Ricardo Martins; Nuno Lourenço; Elisenda Roca; Ricardo Filipe Sereno Póvoa; António Canelas; Rafael Castro-López; Nuno Horta; Francisco Fernández. "Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology". Integration, The VLSI Journal 63 n/a (2018): 351-361. http://www.it.pt/Publications/PaperJournal/27961.
    10.1016/j.vlsi.2018.02.005
  28. Ricardo Martins; Nuno Lourenço; Fábio Passos; Ricardo Filipe Sereno Póvoa; António Canelas; Elisenda Roca; Rafael Castro-López; et al. "Two-Step RF IC Block Synthesis with Pre-Optimized Inductors and Full Layout Generation In-the-loop". IEEE Transactions on Computer-Aided Design Early Acce Early Acce (2018): Early Access-Early Access. http://www.it.pt/Publications/PaperJournal/27960.
    10.1109/TCAD.2018.2834394
  29. Ricardo Filipe Sereno Póvoa; Nuno Lourenço; Ricardo Martins; António Canelas; Nuno Horta; João Goes. "Single Stage OTA biased by Voltage-Combiners with Enhanced Performance using Current Starving". IEEE Transactions on Circuits and Systems II: Express Briefs 1 1 (2017): 1-5. http://www.it.pt/Publications/PaperJournal/23723.
    10.1109/TCSII.2017.2777533
  30. Ricardo Martins; Nuno Lourenço; António Canelas; Nuno Horta. "Stochastic-based placement template generator for analog IC layout-aware synthesis". Integration, The VLSI Journal 58 n/a (2017): 485-495. http://www.it.pt/Publications/PaperJournal/22639.
    10.1016/j.vlsi.2017.02.012
  31. Ricardo Filipe Sereno Póvoa; Nuno Lourenço; Ricardo Martins; António Canelas; Nuno Horta; João Goes. "Single-Stage Amplifier biased by Voltage-Combiners with Gain and Energy-Efficiency Enhancement". IEEE Transactions on Circuits and Systems II: Express Briefs PP 99 (2017): 1-1. http://www.it.pt/Publications/PaperJournal/22648.
    10.1109/TCSII.2017.2686586
  32. Martins, Ricardo. "Current-flow & Current-Density-aware Multi-Objective Optimization of Analog IC Placement". Integration, the VLSI Journal (2016):
    10.1016/j.vlsi.2016.05.008
  33. Lourenço, N.; Martins, R.; Canelas, A.; Póvoa, R.; Horta, N.. "AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation". Integration, the VLSI Journal (2016): http://www.scopus.com/inward/record.url?eid=2-s2.0-84966648845&partnerID=MN8TOARS.
    10.1016/j.vlsi.2016.04.009
  34. Martins, R.; Lourenço, N.; Horta, N.. "Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates". Expert Systems with Applications 42 23 (2015): 9137-9151. http://www.scopus.com/inward/record.url?eid=2-s2.0-84940827353&partnerID=MN8TOARS.
    10.1016/j.eswa.2015.08.020
  35. Martins, R.; Lourenço, N.; Canelas, A.; Horta, N.. "Electromigration-aware analog Router with multilayer multiport terminal structures". Integration, the VLSI Journal 47 4 (2014): 532-547. http://www.scopus.com/inward/record.url?eid=2-s2.0-84903315430&partnerID=MN8TOARS.
    10.1016/j.vlsi.2014.02.003
  36. Martins, R.; Lourenço, N.; Horta, N.. "Routing analog ICs using a multi-objective multi-constraint evolutionary approach". Analog Integrated Circuits and Signal Processing 78 1 (2014): 123-135. http://www.scopus.com/inward/record.url?eid=2-s2.0-84892669296&partnerID=MN8TOARS.
    10.1007/s10470-013-0088-9
  37. Lourenço, N.; Canelas, A.; Póvoa, R.; Martins, R.; Horta, N.. "Floorplan-aware analog IC sizing and optimization based on topological constraints". Integration, the VLSI Journal (2014): http://www.scopus.com/inward/record.url?eid=2-s2.0-84906072112&partnerID=MN8TOARS.
    10.1016/j.vlsi.2014.07.002
  38. Martins, R.; Lourenço, N.; Horta, N.. "LAYGEN II-automatic layout generation of analog integrated circuits". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32 11 (2013): 1641-1654. http://www.scopus.com/inward/record.url?eid=2-s2.0-84886665180&partnerID=MN8TOARS.
    10.1109/TCAD.2013.2269050
Journal issue
  1. Martins, Ricardo. "Special Issue on Selected Papers from PRIME and SMACD 2023". International Journal of Electronics and Communications (2024):
    Under revision • Invited editor
  2. Martins, Ricardo. "Special Issue Selected Papers from PRIME and SMACD 2022". Integration, the VLSI (2023):
    Published • Editor
  3. Martins, Ricardo; Lourenço, Nuno; Fábio Moreira de Passos. "Special Issue on Advanced Design Techniques and EDA Methodologies for Analog, RF, and mm-Wave Circuit Design". Electronics MDPI (2023):
    Published • Invited editor
  4. Martins, Ricardo. "Special Issue on Selected Papers from PRIME and SMACD 2019". Integration, the VLSI (2020):
    Published • Editor
Preface / Postscript
  1. Martins, Ricardo. "2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)". United States: IEEE. 2019.
    Published
Preprint
  1. Ricardo M. F. Martins. "A Survey of Machine and Deep Learning Techniques in Analog Integrated Circuit Layout Synthesis". 2025. https://doi.org/10.20944/preprints202503.2119.v1.
    10.20944/preprints202503.2119.v1
Thesis / Dissertation
  1. Martins, Ricardo. "Placement, Routing and Parasitic Extraction Techniques applied to Analog IC Design Automation". PhD, Universidade de Lisboa Instituto Superior Técnico, 2015.
  2. Martins, Ricardo. "LAYGEN II - Automatic Layout Generation of Analog ICs based on Template Descriptions and Evolutionary Computation". Master, Universidade de Lisboa Instituto Superior Técnico, 2012.

Other

Other output
  1. UMC 110nm Integrated Circuit Prototype. Europractice UMC 110nm. LNA for EMG and EOG, Fully Integrated Inductive DCDC converter. 2021. Nuno Lourenço; Pedro Santos; Rafael Vieira; Ricardo Martins; Ricardo Povoa.
  2. Managing editor of the Proceedings of the International Conference on SMACD 2019. Proceedings of the International Conference on SMACD 2019, published on IEEE Xplore DOI: 10.1109/SMACD46049.2019. 2019. Martins, Ricardo. https://ieeexplore.ieee.org/servlet/opac?punumber=8786808.
  3. AMS0.35µm Integrated Circuit Prototype. Europractice AMS 0.35µm.. 2017. Fábio Passos; Nuno Lourenço; Martins, Ricardo.
  4. UMC0.13µm Integrated Circuit Prototype. Europractice UMC L13077146/R14120/02. 2016. Ricardo Povoa; Nuno Lourenço; Ricardo Martins.
Activities

Oral presentation

Presentation title Event name
Host (Event location)
2022/07 Accelerating Voltage-Controlled Oscillator Sizing Optimizations with ANN-based Convergence Classifiers and Frequency Guess Predictors International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design 2022
(Sardinia)
2022/05 Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator based on ANNs IEEE International Symposium on Circuits and Systems (ISCAS) 2022
(Austin, United States)
2022/05 Automatic Design of High-Gain 26.5-to-29.5-GHz Transformer-Less Low-Noise Amplifier 1.86-to-8.87-mW Variants in 65-nm CMOS IEEE International Symposium on Circuits and Systems (ISCAS) 2022
(Austin, United States)
2021/12 Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement Design Automation Conference (DAC) 2021
(São Francisco, United States)
2021/07 An Essay on the Next Generation of Performance-driven Analog/RF IC EDA Tools: The Role of Simulation-based Layout Optimization International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design 2021
(Erfurt, Germany)
2020/10 Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender IEEE International Symposium on Circuits and Systems (ISCAS)
(Seville, Spain)
2020/08 Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools IEEE International Symposium on Integrated Circuits and Systems (ISICAS)
(Paris, France)
2018/07 Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (Prague, Czech Republic)
2017/06 Layout-Aware Challenges and a Solution for the Automatic Synthesis of Radio-Frequency IC Blocks International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (Giardini Naxos, Italy)
2016/06 On-the-fly Exploration of Placement Templates for Analog IC Layout-aware Sizing Methodologies International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (Lisbon, Portugal)
2015/11 Embedding Fault List Compression Techniques in a Design Automation Framework for Analog and Mixed-Signal Structural Testing Conference on Design of Circuits and Integrated Systems (DCIS)
Conference on Design of Circuits and Integrated Systems (DCIS) (Estoril, Portugal)
2015/09 AIDA: Robust Layout-aware Synthesis of Analog ICs including Sizing and Layout Generation Design Automation Competition
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (Istanbul, Turkey)
2015/09 Exploring Design Tradeoffs in Analog IC Placement with Current-flow & Current-density Considerations International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (Istanbul, Turkey)
2015/06 Analog IC Placement using Absolute Coordinates and a Hierarchical Combination of Pareto Optimal Fronts IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME)
IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME) (Glasgow, United Kingdom)
2015/06 AIDA-PEx: Accurate Parasitic Extraction for Layout-Aware Analog Integrated Circuit Sizing IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME)
IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME) (Glasgow, United Kingdom)
2015/05 Extraction and Application of Wiring Symmetry Rules to Route Analog Multiport Terminals IEEE International Symposium on Circuits and Systems (IEEE ISCAS)
IEEE International Symposium on Circuits and Systems (IEEE ISCAS) (Lisbon, Portugal)
2014/03 Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures Design, Automation & Test in Europe (DATE) Conference
Design, Automation & Test in Europe (DATE) Conference (Dresden, Germany)
2012/09 Multi-Objective Multi-Constraint Routing of Analog ICs using a Modified NSGA-II Approach International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (Seville, Spain)
2012/07 Human-competitive Analog IC Layout Generation “Humies Competition” (Human-Competitive Results Produced by Genetic and Evolutionary Computation)
Genetic and Evolutionary Computation Conference (Philadelphia, United States)
2012/07 LAYGEN II - Automatic Analog ICs Layout Generator based on a Template Approach Genetic and Evolutionary Computation Conference
Genetic and Evolutionary Computation Conference (Philadelphia, United States)

Supervision

Thesis Title
Role 		Degree Subject (Type)
Institution / Organization
2025/01/01 - 2028/12/31 Design Automation of Power Management Units in Deep Nanometer Technologies
Supervisor
 Doctoral Degree Program in ECE (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2024/01 - 2026/12 Generative AI Solutions for Analog Integrated Circuits Design
Supervisor
 Engenharia Electrotécnica e de Computadores (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2025/01/01 - 2025/12/31 A Study of Different VAE-MLP-based Architectures for Post-layout Performance Prediction of Analog Integrated Circuits
Supervisor
 Master’s degree in ECE of UL/UShanghai (MEEC-SHU) (Master)
Shanghai University, China
2025/01 - 2025/12 Using Variational Autoencoders to Address the Inverse Sizing Design Problem of Analog Integrated Circuits
Supervisor
 Master’s degree in ECE of UL/UShanghai (MEEC-SHU) (Master)
Shanghai University, China
2024/02 - 2025/04 Agents that Design Circuits: Reinforcement Learning approach to Analog Integrated Circuit Design Automation
Co-supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2024/02 - 2025/04 Assisting Interconnects' Drawing with Predictive Machine/Deep Learning
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2023/09 - 2024/10 Ensemble Machine/Deep Learning for Performance Prediction
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2023/09 - 2024/10 Generative Artificial Intelligence for Analog Integrated Circuit Design Automation
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2023/09 - 2024/10 Layout design automation for power devices
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2023/09 - 2024/04 Improving Sampling Efficiency of Multi-Net Multi-Terminal Analog Integrated Circuit Routing with Machine Learning
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020/04 - 2023/12 Deep Learning Techniques for End-to-end Deep Nanometer Analog and Radio Frequency Integrated Circuit Design Automation
Supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020/09 - 2021/10 ANN-based Floorplan Recommender for Large Analog IC Building Blocks with Multiple Topological Constraints Coverage
Supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020/09 - 2021/10 Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator using Deep ANNs
Supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020/09 - 2021/10 Accelerating Voltage-Controlled Oscillator Sizing Optimizations with a Convergence Classifier & Frequency Guess Predictor
Supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2019/02 - 2019/10 Semi-Supervised Artificial Neural Networks towards Push-Button Analog IC Placement
Supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/02 - 2018/10 EDA to the cloud: a case study to increase both effectiveness and user experience of EDA tools
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/02 - 2018/10 On the Exploration of Automatic Analog Integrated Circuit Placement using Neural Networks
Supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/09 - 2018/06 Using Artificial Neural Networks to Size Analog Integrated Circuits
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/02 - 2017/11 Enhanced Analog and RF IC Sizing Methodology using PCA and NSGA-II Optimization Kernel
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2014/09 - 2015/05 AIDA-PEx: Parasitic Extraction on Layout-Aware Analog Integrated Circuit Sizing
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal

Event organisation

Event name
Type of event (Role) 		Institution / Organization
2022 - Current SMACD 2022 Technical Program Chair (2022/06)
Conference (Co-organisor)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design 2022, Italy
2021 - Current SMACD 2021 Technical Program Chair (2020 - 2021/07)
Conference (Co-organisor)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2021, Germany
2024/03 - 2024/03 Technical Program Committee of the Design Automation and Test in Europe Conference (2024/03 - 2024/03)
Conference (Member of the Scientific Committee)
2016 - 2024 SMACD Technical Program Committee (2016 - 2024)
Conference (Member of the Scientific Committee)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2016, 2017, 2018, 2019, 2021, Germany
2016 - 2024 PRIME Technical Program Committee (2016 - 2024)
Conference (Member of the Scientific Committee)
 IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME) 2016, 2017, 2018, 2019, 2021, Germany
2023/01 - 2023/07 SMACD 2023 Technical Program Chair (2023/07/03 - 2023/07/05)
Conference (Co-organisor)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD) 2023, Portugal
2023/01 - 2023/01 Technical Program Committee of the Asia and South Pacific Design Automation Conference (2023/01 - 2023/01)
Conference (Member of the Scientific Committee)
2019 - 2019 SMACD 2019 General Chair (2019/07 - 2019/07)
Conference (President of the Organising Committee)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2019 Committee, Switzerland
2019 - 2019 IEEE ICECS 2019 Awards Chair (2019/11 - 2019/11)
Conference (Member of the Organising Committee)
 IEEE International Conference on Electronics Circuits and Systems (ICECS) 2019, Italy
2018/07 - 2018/07 SMACD 2018 Special Session Organizer (2018/07 - 2018/07)
Conference (Member of the Organising Committee)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2018 Committee, Czech Republic
2017 - 2017 SMACD 2017 Publication Chair (2017/06 - 2017/06)
Conference (Member of the Organising Committee)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2017 Committee, Italy
2017 - 2017 NGCAS 2017 Competition Chair "Best YP industrial and societal application" (2017/09 - 2017/09)
Conference (Member of the Organising Committee)
 New Generation of Circuits and Systems Conference (NGCAS) 2017, Italy
2016 - 2016 SMACD 2016 Competition Chair "Improve design automation for integrated circuits and systems" (2016/06 - 2016/06)
Conference (Member of the Organising Committee)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2016 Committee, Portugal
2016 - 2016 SMACD 2016 Publication Chair (2016/06 - 2016/06)
Conference (Member of the Organising Committee)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2016 Committee, Portugal
2016 - 2016 PRIME 2016 Publication Chair (2016/06 - 2016/06)
Conference (Member of the Organising Committee)
 Conference on PhD Research in Microelectronics and Electronics (PRIME) 2016, Portugal
2015 - 2015 ISCAS 2015 Local Organizing Committee Member (2015/05 - 2015/05)
Symposium (Other)
 IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Portugal
2014 - 2014 23rd AACD Local Organizing Committee Member (2014/04 - 2014/04)
Workshop (Other)
 23rd Workshop on Advances in Analog Circuit Design , Portugal

Jury of academic degree

Topic
Role 		Candidate name (Type of degree)
Institution / Organization
2022/11 Machine Learning-Based Pairs Trading Strategy with Multivariate Pairs Formed with Multi-objective Optimization
(Thesis) Main arguer
 Miguel Carvalho Figueira (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2021/11 Study of Variability Phenomena on CMOS Technologies for its Mitigation and Exploitation
(Thesis) Main arguer
 Pablo Sarazá Canflanca (PhD)
Universidad de Sevilla, Spain
2019/10 Semi-Supervised Artificial Neural Networks towards Push-Button Analog IC Placement
Supervisor
 António Gusmão (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2019/01 Energy-Efficient Computing: Adaptive Structures and Data Management
(Thesis) Arguer
 Nuno Neves (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/10 On the Exploration of Automatic Analog Integrated Circuit Placement using Neural Networks
Supervisor
 Daniel Guerra (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/05 AIDA-PEx: Parasitic Extraction on Layout-Aware Analog Integrated Circuit Sizing
Supervisor
 Bruno Cardoso (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal

Committee member

Activity description
Role 		Institution / Organization
2019 - Current SMACD 2021 Steering Committee
Member
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2021, Germany

Conference scientific committee

Conference name Conference host
2016 - Current Conference on PhD Research in Microelectronics and Electronics Several Editions
2016 - Current International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design Several Editions
2015 - 2021 IEEE International Symposium on Circuits and Systems Several Editions
2019 - 2019 IEEE International Conference on Electronics Circuits and Systems Genova, Italy
2018 - 2018 IEEE Computer Society Annual Symposium on VLSI Hong Kong, China
2017 - 2017 1st Conference on New Generation of Circuits and Systems Genova, Italy

Course / Discipline taught

Academic session Degree Subject (Type) Institution / Organization
2024/02 - Current Circuits Theory and Electronic Fundamentals (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2023/09 - Current Ultra-Low Power Circuits Engenharia Electrotécnica e de Computadores (Mestrado) Universidade de Lisboa Instituto Superior Técnico, Portugal
2023/04 - Current Electronic Circuits Engenharia Electrotécnica e de Computadores (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2023/02 - Current Instrumentation and Measurements Engenharia Electrotécnica e de Computadores (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2016 - 2019 Systems Programming Engenharia Electrotécnica e de Computadores (Mestrado integrado) Universidade de Lisboa Instituto Superior Técnico, Portugal
2015 - 2016 Computer Architecture Engenharia Electrotécnica e de Computadores (Mestrado integrado) Universidade de Lisboa Instituto Superior Técnico, Portugal
2012 - 2013 Digital Systems Engenharia Electrotécnica e de Computadores (Mestrado integrado) Universidade de Lisboa Instituto Superior Técnico, Portugal

Journal scientific committee

Journal title (ISSN) Publisher
2020 - Current Electronics Open Access Journal (2079-9292) MDPI
2016 - Current IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems (0278-0070) IEEE
2020 - 2021 Mathematical and Computational Applications Open Access Journal (2297-8747) MDPI
2017 - 2021 IEEE Transactions on Circuits and Systems I: Regular Papers (1549-8328) IEEE
2016 - 2021 Turkish Journal of Electrical Engineering & Computer Sciences (1300-0632) Tübitak
2016 - 2021 Applied Soft Computing (1568-4946) Elsevier
2015 - 2021 IET Computers & Digital Techniques Journal (0143-7062) IET Digital Library
2015 - 2021 Integration, the VLSI Journal (0167-9260) Elsevier
Distinctions

Award

2023 SMACD 2023 1st Place on "IC Design Contest" (1000USD award)
2021 3rd Place on SMACD "Design Automation Competition"
2019 SMACD 2019 Best Paper Award Runner-Up
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2019 Committee, Switzerland
2019 Integration, the VLSI Journal 2019 Best Paper Award
Integration, the VLSI Journal, Elsevier, Netherlands
2018 SMACD 2018 Best Paper Award
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2018 Committee, Czech Republic
2016 SMACD 2016 Best Paper Award
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2016 Committee, Portugal
2015 PRIME 2015 Silver Leaf Best Paper Award
IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME) 2015 Committee, United Kingdom
2015 1st Ranked on SMACD "Design Automation Competition" (1000USD prize)
2014 ISCAS 2014 Student Best Paper Award Runner-Up
IEEE International Symposium on Circuits and Systems (ISCAS) 2015 Committee, Australia

Other distinction

2022 SMACD 2022 Best Paper Award Nominee
2022 SMACD 2022 Best Paper Award Runner-Up
2020 IST Outstanding Teaching Award
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018 IST Outstanding Teaching Award
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 SMACD 2017 Best Paper Award Nominee
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2017 Committee, Italy
2014 IST Outstanding Teaching Award
Universidade de Lisboa Instituto Superior Técnico, Portugal
2012 Finalist of the GECCO "Humies Competition"
Genetic and Evolutionary Computation Conference (GECCO) 2012 Committee, United States
2012 Honorable Mention from SMACD "Design Automation Competition"
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2012 Committee, Spain