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Nuno Filipe Valentim Roma holds a Ph.D. in Electrical and Computer Engineering, awarded on 2008/05/05 by Universidade de Lisboa - Instituto Superior Técnico. He also holds an M.Sc. in Electrical and Computer Engineering, awarded on 2001/05/09, and a Degree in Electrical and Computer Engineering, awarded on 1998/12/21, both from Universidade de Lisboa Instituto Superior Técnico. He is an Associate Professor with the Department of Electrical and Computer Engineering at Universidade de Lisboa - Instituto Superior Técnico. Dr. Roma has authored 149 peer-reviewed manuscripts, including 4 book chapters, 46 articles in scientific journals, and 85 papers at international conferences. Additionally, he has presented 14 papers at national conferences. In the academic realm, he has supervised 5 Ph.D. theses and co-supervised 5 others. He has received 4 awards and/or honors for his research work. Actively engaged in research, he has participated as the Principal Investigator in 3 projects and as a Researcher in 8 others, all within the domain of Engineering and Technology. His expertise lies in Electrotechnical Engineering, Electronics, and Informatics, particularly focusing on Computer Hardware and Architecture. Throughout his professional journey, Dr. Roma has collaborated with 134 individuals, co-authoring numerous scientific papers. In his curriculum Ciência Vitae the most frequent terms in the context of scientific, technological and artistic-cultural output are: Aprendizagem Profunda; Processadores Dedicados e Especializados; Processamento Paralelo; Adders; Computer architecture; Power dissipation; Video coding; Encoding; Streaming media; Hardware; Approximate computing; imprecise adders; SAD; video coding; power efficiency; cache storage; microprocessor chips; memory hierarchy; intrinsic parallelism; data locality; execution time; processing cores; cache structures; multilevel cache subsystem; current processors; average memory access time; memory bound vector operations; Compute caches; Xilinx Virtex-7 VC709 Development Board; MB-Lite soft-core; vector compute units; data transfers; long cache lines; memory-bound kernels; Cache Compute System; Program processors; Registers; Parallel processing; Programming; Indexes; Memory bound operations; Vectorization; Compiler-based Abstractions; Unified Computing; Adaptable Hardware; Stream Computing; transformação digital e cidadania; tecnologias da vida e saúde; transição energética; segurança e privacidade; Sistemas Electrónicos; Sistemas de Informação; Sistemas e Redes de Computadores; Sistemas Multimédia Inteligentes; 3D Reconstruction; Visual-Inertial Simultaneous Localization and Mapping; Domain-Specific Architectures; Low-Power Embedded Accelerators; .
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Identification

Personal identification

Full name
Nuno Filipe Valentim Roma

Citation names

  • Roma, Nuno

Author identifiers

Ciência ID
CB11-EDBA-7BA5
ORCID iD
0000-0003-2491-4977
Google Scholar ID
iDxEJwIAAAAJ
Researcher Id
C-5586-2008
Scopus Author Id
6602399540

Knowledge fields

  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Computer Hardware and Architecture

Languages

Language Speaking Reading Writing Listening Peer-review
Portuguese Advanced (C1) Advanced (C1) Advanced (C1) Advanced (C1)
English Intermediate (B1) Advanced (C1) Intermediate (B1) Intermediate (B1)
Education
Degree Classification
2008/05/05
Concluded
 Ph.D. in Electrical and Computer (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Dedicated Processors for Motion Estimation in Video Sequences" (THESIS/DISSERTATION)
 Unanimously aproved
2001/05/09
Concluded
 M.Sc. in Electrical and Computer Engineering (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Dedicated Processors for Motion Estimation in Video Sequences" (THESIS/DISSERTATION)
 Very Good
1998/12/21
Concluded
 Degree in Electrical and Computer Engineering (Licenciatura)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Digital Video Transmission through the Electrical Power Lines" (THESIS/DISSERTATION)
 18 (in a 0-20 scale)
Affiliation

Teaching in Higher Education

Category
Host institution 		Employer
2020/11/01 - Current Associate Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
2008/06/13 - 2020/10/31 Assistant Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
2003/09/15 - 2008/06/12 Assistant (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
Projects

Contract

Designation Funders
2023/03/10 - 2026/03/09 Compilation Abstraction and Hardware Adaptation for Specialized and General-Purpose Computing Unification
2022.06780.PTDC
10.54499/2022.06780.PTDC
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Ongoing
2021/01/01 - 2025/12/31 Instituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento em Lisboa
LA/P/0078/2020
10.54499/LA/P/0078/2020
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Ongoing
2023/03/10 - 2024/09/09 Accelerator Framework for Real-Time 3D Reconstruction of Underwater Caves
2022.04020.PTDC
10.54499/2022.04020.PTDC
Universidade de Lisboa Instituto de Sistemas e Robótica, Portugal

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Fundação para a Ciência e a Tecnologia
Ongoing
2020/01/01 - 2022/12/31 ResNetDetect: Deteção Automática Precoce de Incêndios Florestais Utilizando Redes Neuronais de Aprendizagem Residual
PCIF/MPG/0051/2018
Researcher
INOV INESC INOVAÇÃO - Instituto de Novas Tecnologias, Portugal
 Fundação para a Ciência e a Tecnologia
Ongoing
2018/12/01 - 2021/11/30 European Processor Initiative (Specific Grant Agreement 1)
826647
Researcher
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/07/16 - 2021/07/15 HAnDLE: Hardware Accelerated Deep Learning Framework
PTDC/EEI-HAC/30485/2017
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Ongoing
2014/04 - 2017/04 EMC2: Embedded Multi-Core Systems for Mixed Criticality Applications in Dynamic and Changeable Real-Time Environments
SP1-JTI-ARTEMIS-2013-AIPP5
Researcher
Fundação para a Ciência e a Tecnologia, I.P.
2013/05 - 2015/04 Stretching the Limits of Parallel Processing on Heterogenous Computing Systems
129304
Provided by PTCRIS: 129304
Researcher
Fundação para a Ciência e a Tecnologia, I.P.
2012/03 - 2015/02 THREadS: Multitask System Framework with Transparent Hardware Reconfiguration
Provided by PTCRIS: 117329
117329
Researcher
Fundação para a Ciência e a Tecnologia, I.P.
2011/01 - 2013/12 TAGS : The power of the short - Tools and Algorithms for next Generation Sequencing applications
112283
Provided by PTCRIS: 112283
Researcher
Fundação para a Ciência e a Tecnologia, I.P.
2011/01 - 2013/12 HELIX: Heterogeneous Multi-Core Architecture for Biological Sequence Analysis
Provided by PTCRIS: 113999
113999
Principal investigator
Fundação para a Ciência e a Tecnologia, I.P.
2011/01/01 - 2012/12/31 Projecto Estratégico - LA 21 - 2011-2012
PEst-OE/EEI/LA0021/2011
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2007/07 - 2010/12 IDeA - Integrated Design for Automation of Anaesthesia
69288
Provided by PTCRIS: 69288
Researcher
Fundação para a Ciência e a Tecnologia, I.P.
2005/01 - 2008/11 AMEP: Adaptive H.264/AVC Motion Estimation Processor for Mobile and Battery Supplied Devices
60765
Provided by PTCRIS: 60765
Researcher
Fundação para a Ciência e a Tecnologia, I.P.
Outputs

Publications

Book
  1. Sousa, L.; Roma, N.; Tomás, P.. Preface. 2021.
  2. Pinheiro, R.; Roma, N.; Tomás, P.. A cross-core performance model for heterogeneous many-core architectures. 2017.
    10.1007/978-3-319-61982-8_11
  3. Neves, N.; Mussio, A.; Gonçalves, F.; Tomás, P.; Roma, N.. In-cache streaming: Morphable infrastructure for many-core processing systems. 2017.
    10.1007/978-3-319-58943-5_62
  4. Guerreiro, J.; Ilic, A.; Roma, N.; Tomás, P.. Performance and power-aware classification for frequency scaling of GPGPU applications. 2017.
    10.1007/978-3-319-58943-5_11
  5. Roma, N.; Rodrigues, A.; Sousa, L.. Parallel Programming Framework for H.264/AVC Video Encoding in Multicore Systems. 2017.
    10.1002/9781119332015.ch14
  6. Cruz, M.T.; Tomás, P.; Roma, N.. Energy-efficient architecture for DP local sequence alignment: Exploiting ILP and DLP. 2015.
    10.1007/978-3-319-16480-9_20
  7. Ferreirinha, T.; Nunes, R.; Soares, A.; Pratas, F.; Tomás, P.; Roma, N.. GPU accelerated stochastic inversion of deep water seismic data. 2014.
    10.1007/978-3-319-14325-5_21
  8. Colaço, J.; Matoga, A.; Ilic, A.; Roma, N.; Tomás, P.; Chaves, R.. Transparent application acceleration by intelligent scheduling of shared library calls on heterogeneous systems. 2014.
    10.1007/978-3-642-55224-3_65
  9. Momcilovic, S.; Roma, N.; Sousa, L.. Multi-level parallelization of advanced video coding on hybrid CPU+GPU platforms. 2013.
    10.1007/978-3-642-36949-0_19
  10. Dias, T.; Roma, N.; Sousa, L.. Low power distance measurement unit for real-time hardware motion estimators. 2006.
    10.1007/11847083_24
  11. Roma, N.; Dias, T.; Sousa, L.. Customizable and reduced hardware motion estimation processors. 2005.
    10.1007/1-4020-3128-9_5
  12. Roma, N.; Dias, T.; Sousa, L.. Customisable core-based architectures for real-time motion estimation on FPGAs. 2003.
Book chapter
  1. Malcata, Tomás; Sebastião, Nuno; Dias, Tiago; Roma, Nuno. "Neural Network Predictor for Fast Channel Change on DVB Set-Top-Boxes". In Design and Architecture for Signal and Image Processing, 40-52. Springer Nature Switzerland, 2023.
    10.1007/978-3-031-29970-4_4
  2. Roma, Nuno. "A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation". 2002.
    10.1007/978-0-387-35597-9_22
Conference paper
  1. Joao Mario Domingos; Tiago Rocha; Nuno Neves; Nuno Roma; Pedro Tomás; Leonel Sousa. "Supporting RISC-V Performance Counters Through Linux Performance Analysis Tools". 2023.
    10.1109/asap57973.2023.00027
  2. Crespo, L.; Tomas, P.; Roma, N.; Neves, N.. "Trading Performance, Power, and Area on Low-Precision Posit MAC Units for CNN Training". 2023.
    10.1109/SBAC-PAD59825.2023.00014
  3. Storch, I.; Roma, N.; Palomino, D.; Bampi, S.. "GPU Acceleration of MIP Intra Prediction in VVC". 2023.
    10.23919/EUSIPCO58844.2023.10290037
  4. Joao Vieira; Nuno Roma; Gabriel Falcao; Pedro Tomas. "gem5-ndp: Near-Data Processing Architecture Simulation From Low Level Caches to DRAM". 2022.
    10.1109/sbac-pad55451.2022.00015
  5. Crespo, Luis; Neves, Nuno; Tomás, Pedro; Roma, Nuno. "Unified Posit/IEEE-754 Vector Mac Unit for Transprecision Computing". Paper presented in IEEE International Symposium on Circuits & Systems (ISCAS’2022), Austin, 2022.
    Accepted
  6. Marcel Moscarelli Corrêa; Roma, Nuno; Daniel Palomimo; Guilherme Corrêa; Luciano Agostini. "Mode-Adaptive Subsampling of SAD/SSE Operations for Intra Prediction Cost Reduction". Paper presented in IEEE International Symposium on Circuits & Systems (ISCAS’2022), Austin, 2022.
    Accepted
  7. Correa, M.; Roma, N.; Palomino, D.; Correa, G.; Agostini, L.. "Mode-Adaptive Subsampling of SAD/SSE Operations for Intra Prediction Cost Reduction". 2022.
    10.1109/ISCAS48785.2022.9937507
  8. Rosado, M.; Mallios, S.; Tomas, P.; Roma, N.; David, A.. "Early prototyping and testing of CERN LHC CMS high-granularity calorimeter slow-control system". 2022.
    10.1109/RSP57251.2022.10039014
  9. Miguel Pinho; Tomás, Pedro; Roma, Nuno. "Packing and Fusing Narrow-Width Vector Operations for Energy-Efficient SIMD". Paper presented in International Conference on High Performance Computing & Simulation (HPCS’2020), Barcelona, 2021.
    Published
  10. Raposo, G.; Tomás, P.; Roma, N.. "PositNN: Training deep neural networks with mixed low-precision posit". 2021.
    10.1109/ICASSP39728.2021.9413919
  11. Domingos, J.M.; Neves, N.; Roma, N.; Tomas, P.. "Unlimited vector extension with data streaming support". 2021.
    10.1109/ISCA52012.2021.00025
  12. Mendes, F.; Tomas, P.; Roma, N.. "Exploiting non-conventional DVFS on GPUs: Application to deep learning". 2020.
    10.1109/SBAC-PAD49847.2020.00012
  13. Porto, R.; Zatt, B.; Roma, N.; Agostini, L.; Porto, M.. "2PSA: An Optimized and Flexible Power-Precision Scalable Adder". 2020.
    10.1109/SBCCI50935.2020.9189917
  14. Vieira, J.; Roma, N.; Falcao, G.; Tomas, P.. "Processing Convolutional Neural Networks on Cache". 2020.
    10.1109/ICASSP40776.2020.9054326
  15. Neves, N.; Tomas, P.; Roma, N.. "Reconfigurable stream-based tensor unit with variable-precision posit arithmetic". 2020.
    10.1109/ASAP49362.2020.00033
  16. Neves, N.; Tomas, P.; Roma, N.. "Dynamic Fused Multiply-Accumulate Posit Unit with Variable Exponent Size for Low-Precision DSP Applications". 2020.
    10.1109/SiPS50750.2020.9195256
  17. Roger Endrigo Carvalho Porto; Luciano Agostini; Bruno Zatt; Nuno Roma; Marcelo Porto. "Power-Efficient Approximate SAD Architecture with LOA Imprecise Adders". 2019.
    10.1109/LASCAS.2019.8667554
  18. Sá, P.; Aidos, H.; Roma, N.; Tomás, P.. "Heart disease detection architecture for lead I off-the-person ECG monitoring devices". 2019.
    10.23919/EUSIPCO.2019.8902791
  19. Guerreiro, J.; Ilic, A.; Roma, N.; Tomas, P.. "GPGPU Power Modeling for Multi-domain Voltage-Frequency Scaling". 2018.
    10.1109/HPCA.2018.00072
  20. João Vieira; Paolo Ienne; Roma, Nuno; Gabriel Falcao; Pedro Tomás. "Exploiting Compute Caches for Memory Bound Vector Operations". 2018.
    10.1109/CAHPC.2018.8645905
  21. Wang, B.; Alvarez-Mesa, M.; Chi, C.C.; Juurlink, B.; De Souza, D.F.; Ilic, A.; Roma, N.; Sousa, L.. "Efficient HEVC decoder for heterogeneous CPU with GPU systems". 2017.
    10.1109/MMSP.2016.7813353
  22. Porto, R.; Agostini, L.; Zatt, B.; Porto, M.; Roma, N.; Sousa, L.. "Energy-efficient motion estimation with approximate arithmetic". 2017.
    10.1109/MMSP.2017.8122248
  23. Tiago Miguel Braga da Silva Dias; Nuno Roma; Leonel Sousa. "Exploiting Coarse-Grained Parallelism in Multi-Transform Architectures for H.264/AVC High Profile Codecs". Paper presented in 2nd Conference on Electronics, Telecommunications and Computers (CETC), 2016.
    Published
  24. Momcilovic, S.; Roma, N.; Sousa, L.; Milentijevic, I.. "Run-Time Machine Learning for HEVC/H.265 Fast Partitioning Decision". 2016.
    10.1109/ISM.2015.70
  25. De Souza, D.F.; Ilic, A.; Roma, N.; Sousa, L.. "GPU acceleration of the HEVC decoder inter prediction module". 2016.
    10.1109/GlobalSIP.2015.7418397
  26. Cruz, M.T.; Tomás, P.; Roma, N.. "Unsupervised variable-grained online phase clustering for heterogeneous/morphable processors". 2016.
    10.1109/HPCSim.2016.7568424
  27. Roma, Nuno. "Multi-Kernel Auto-Tuning on GPUs: Performance and Energy-Aware Optimization". 2015.
    10.1109/PDP.2015.44
  28. Ferreirinha, T.; Nunes, R.; Azevedo, L.; Soares, A.; Pratas, F.; Tomas, P.; Roma, N.. "Acceleration of stochastic seismic inversion in open cl-based heterogeneous platforms". 2015.
  29. Neves, N.; Tomás, P.; Roma, N.. "Efficient data-stream management for shared-memory many-core systems". 2015.
    10.1109/FPL.2015.7293960
  30. De Souza, D.F.; Ilic, A.; Roma, N.; Sousa, L.. "HEVC in-loop filters GPU parallelization in embedded systems". 2015.
    10.1109/SAMOS.2015.7363667
  31. Dias, T.; Roma, N.; Sousa, L.. "High performance IP core for HEVC quantization". 2015.
    10.1109/ISCAS.2015.7169275
  32. De Souza, D.F.; Ilic, A.; Roma, N.; Sousa, L.. "Towards GPU HEVC intra decoding: Seizing fine-grain parallelism". 2015.
    10.1109/ICME.2015.7177515
  33. Rodrigues, M.; Roma, N.; Tomas, P.. "Fast and scalable thread migration for multi-core architectures". 2015.
    10.1109/EUC.2015.36
  34. Cruz, M.; Tomas, P.; Roma, N.. "Low-power vectorial VLIW architecture for maximum parallelism exploitation of dynamic programming algorithms". 2014.
    10.1109/HPCSim.2014.6903673
  35. De Souza, D.F.; Roma, N.; Sousa, L.. "Opencl parallelization of the HEVC de-quantization and inverse transform for heterogeneous platforms". 2014.
  36. Nogueira, D.; Tomas, P.; Roma, N.. "Burrows-Wheeler Transform based indexed exact search on a multi-GPU OpenCL platform". 2014.
    10.1109/HPCSim.2014.6903666
  37. Ilic, A.; Momcilovic, S.; Roma, N.; Sousa, L.. "FEVES: Framework for efficient parallel video encoding on heterogeneous systems". 2014.
    10.1109/ICPP.2014.11
  38. Momcilovic, S.; Ilic, A.; Roma, N.; Sousa, L.. "Collaborative inter-prediction on CPU+GPU systems". 2014.
    10.1109/ICIP.2014.7025245
  39. De Souza, D.F.; Roma, N.; Sousa, L.. "Cooperative CPU+GPU deblocking filter parallelization for high performance HEVC video codecs". 2014.
    10.1109/ICASSP.2014.6854552
  40. Sebastio, N.; Flores, P.; Roma, N.. "Optimized ASIP architecture for compressed BWT-indexed search in bioinformatics applications". 2014.
    10.1109/HPCSim.2014.6903731
  41. Gorobets, A.; Pratas, F.; Roma, N.; Tomís, P.. "Stream oriented modular architecture with polymorphic processing engines". 2014.
    10.1109/SBAC-PADW.2014.26
  42. Neves, N.; Sebastiao, N.; Patricio, A.; Matos, D.; Tomas, P.; Flores, P.; Roma, N.. "BioBlaze: Multi-core SIMD ASIP for DNA sequence alignment". 2013.
    10.1109/ASAP.2013.6567581
  43. Dias, T.; Roma, N.; Sousa, L.. "High performance multi-standard architecture for DCT computation in H.264/AVC High Profile and HEVC codecs". 2013.
  44. Matoga, A.; Chaves, R.; Tomas, P.; Roma, N.. "A flexible shared library profiler for early estimation of performance gains in heterogeneous systems". 2013.
    10.1109/HPCSim.2013.6641454
  45. Paiágua, S.; Pratas, F.; Tomás, P.; Roma, N.; Chaves, R.. "HotStream: Efficient data streaming of complex patterns to multiple accelerating kernels". 2013.
    10.1109/SBAC-PAD.2013.17
  46. Leitao, J.; Germano, J.; Roma, N.; Chaves, R.; Tomas, P.. "Scalable and high throughput biosensing platform". 2013.
    10.1109/FPL.2013.6645529
  47. Tiago Miguel Braga da Silva Dias; Nuno Roma; Leonel Sousa. "Reconfigurable Unified Architecture for Forward and Inverse Quantization in H.264/AVC". Paper presented in VIII Jornadas sobre Sistemas Reconfiguráveis, 2012.
  48. Dias, T.; Rosário, L.; Roma, N.; Sousa, L.. "High performance unified architecture for forward and inverse quantization in H.264/AVC". 2012.
    10.1109/DSD.2012.73
  49. Roma, N.; Magalhães, P.. "System-level prototyping framework for heterogeneous multi-Core architecture applied to biological sequence analysis". 2012.
    10.1109/RSP.2012.6380705
  50. Tiago Miguel Braga da Silva Dias; Nuno Roma; Leonel Sousa. "Optimized Forward/Inverse Quantization Unit for H.264/AVC Codecs". Paper presented in Conference on Electronics, Telecommunications and Computers, 2011.
  51. Tiago Miguel Braga da Silva Dias; Nuno Roma; Leonel Sousa. "Efficient and Programmable Processing Unit for H.264/AVC Systolic Unified Transform Engines". Paper presented in VII Jornadas sobre Sistemas Reconfiguráveis, 2011.
    Published
  52. Dias, T.; Lopez, S.; Roma, N.; Sousa, L.. "High throughput and scalable architecture for unified transform coding in embedded H.264/AVC video coding systems". 2011.
    10.1109/SAMOS.2011.6045465
  53. Encarnação, G.; Sebastião, N.; Roma, N.. "Advantages and GPU implementation of high-performance indexed DNA search based on suffix arrays". 2011.
    10.1109/HPCSim.2011.5999806
  54. Almeida, T.; Roma, N.. "A parallel programming framework for multi-core DNA sequence alignment". 2010.
    10.1109/CISIS.2010.100
  55. Dias, T.; Roma, N.; Sousa, L.. "Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems". 2010.
    10.1109/DASIP.2010.5706271
  56. Dias, T.; Roma, N.; Sousa, L.. "H.264/AVC framework for multi-core embedded video encoders". 2010.
    10.1109/ISSOC.2010.5625538
  57. Rodrigues, A.; Roma, N.; Sousa, L.. "p264: Open platform for designing parallel H.264/AVC video encoders on multi-core systems". 2010.
    10.1145/1806565.1806586
  58. Sebastião, N.; Dias, T.; Roma, N.; Flores, P.. "Integrated accelerator architecture for DNA sequences alignment with enhanced traceback phase". 2010.
    10.1109/HPCS.2010.5547154
  59. Passos, G.; Roma, N.; Da Costa, B.A.; Sousa, L.; Lemos, J.M.. "Distributed software platform for automation and control of general anaesthesia". 2009.
    10.1109/ISPDC.2009.34
  60. Nuno Sebastião; Tiago Miguel Braga da Silva Dias; Nuno Roma; Paulo Flores; Leonel Sousa. "Specialized Motion Estimation Processor for Heterogeneous Multicore Video Coding Systems". Paper presented in 4th International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems, 2008.
    Published
  61. Tiago Miguel Braga da Silva ; Nuno Sebastião; Nuno Roma; Paulo Flores; Leonel Augusto Pires Seabra de Sousa. "Programmable IP core for motion estimation: comparison of FPGA and ASIC based implementations". Paper presented in IV Jornadas sobre Sistemas Reconfiguráveis, 2008.
  62. Sebastião, N.; Dias, T.; Roma, N.; Flores, P.; Sousa, L.. "Application specific programmable IP core for motion estimation: Technology comparison targeting efficient embedded co-processing units". 2008.
    10.1109/DSD.2008.66
  63. Momcilovic, S.; Roma, N.; Sousa, L.. "Adaptive motion estimation algorithm for H.264/AVC". 2007.
    10.1109/ICDSP.2007.4288633
  64. Momcilovic, S.; Roma, N.; Sousa, L.. "An ASIP approach for adaptive AVC motion estimation". 2007.
    10.1109/RME.2007.4401838
  65. Roma, N.; Sousa, L.. "Fully compressed-domain transcoder for PIP/PAP video composition". 2007.
  66. Momcilovic, S.; Dias, T.; Roma, N.; Sousa, L.. "Application specific instruction set processor for adaptive video motion estimation". 2006.
    10.1109/DSD.2006.25
  67. Tiago Miguel Braga da Silva Dias; Nuno Roma; Leonel Sousa. "Fully Parameterizable VLSI Architecture for Sub-Pixel Motion Estimation with Low Memory Bandwidth Requirements". Paper presented in 3ª Jornadas de Engenharia de Electrónica e Telecomunicações e de Computadores, 2005.
  68. Tiago Miguel Braga da Silva Dias; Nuno Roma; Leonel Sousa. "Two-Level Scalable Motion Estimation Architecture with Fractional-Pixel Accuracy and Efficient Data Re-Usage". Paper presented in Jornadas sobre Sistemas Reconfiguráveis, 2005.
  69. Dias, T.; Roma, N.; Sousa, L.. "Efficient VLSI architecture for real-time motion estimation in advanced video coding". 2005.
  70. Dias, T.; Roma, N.; Sousa, L.. "Efficient motion vector refinement architecture for sub-pixel motion estimation systems". 2005.
    10.1109/SIPS.2005.1579885
  71. Roma, N.; Sousa, L.. "Least squares motion estimation algorithm in the compressed DCT domain for H.26x / MPEG-x video sequences". 2005.
    10.1109/AVSS.2005.1577332
  72. Nuno Roma; Tiago Miguel Braga da Silva Dias; Leonel Sousa. "Fast Adder Architectures: Modeling and Experimental Evaluation". Paper presented in XVIII Conference on Design of Circuits and Integrated Systems, 2003.
  73. Roma, Nuno. "Insertion of Irregular-Shaped Logos in the Compressed DCT Domain". 2002.
    10.1109/ICDSP.2002.1027848
  74. Roma, N.; Sousa, L.. "Parameterizable hardware architectures for automatic synthesis of motion estimation processors". 2001.
  75. Roma, Nuno; Sousa, Leonel. "In the development and evaluation of specialized processors for computing high-order 2-D image moments in real-time". 2000.
  76. Roma, Nuno. "Low-Power Array Architectures for Motion Estimation". 1999.
    10.1109/MMSP.1999.793944
Journal article
  1. João Vieira; Nuno Roma; Gabriel Falcao; Pedro Tomás. "gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation". IEEE Computer Architecture Letters (2024): https://doi.org/10.1109/LCA.2023.3329443.
    10.1109/LCA.2023.3329443
  2. João Vieira; Nuno Roma; Gabriel Falcao; Pedro Tomás. "NDPmulator: Enabling Full-System Simulation for Near-Data Accelerators From Caches to DRAM". IEEE Access (2024): https://doi.org/10.1109/ACCESS.2024.3352924.
    10.1109/ACCESS.2024.3352924
  3. Nuno Roma; Bruno Zatt. "SBCCI 2022". IEEE Design & Test (2023): https://doi.org/10.1109/MDAT.2023.3291688.
    10.1109/MDAT.2023.3291688
  4. Saha, Anup; Roma, Nuno; Chavarrías, Miguel; Dias, Tiago; Pescador, Fernando; Aranda, Víctor. "GPU-based parallelisation of a versatile video coding adaptive loop filter in resource-constrained heterogeneous embedded platform". Journal of Real-Time Image Processing 20 3 (2023): http://dx.doi.org/10.1007/s11554-023-01300-z.
    10.1007/s11554-023-01300-z
  5. Nuno Neves; Joao Mario Domingos; Nuno Roma; Pedro Tomas; Gabriel Falcao. "Compiling for Vector Extensions With Stream-Based Specialization". IEEE Micro (2022): https://doi.org/10.1109/MM.2022.3173405.
    10.1109/MM.2022.3173405
  6. Francisco Mendes; Pedro Tomás; Nuno Roma. "Decoupling GPGPU voltage-frequency scaling for deep-learning applications". Journal of Parallel and Distributed Computing (2022): https://doi.org/10.1016/j.jpdc.2022.03.004.
    10.1016/j.jpdc.2022.03.004
  7. Crespo, L.; Roma, P.T.N.; Neves, N.. "Unified Posit/IEEE-754 Vector MAC Unit for Transprecision Computing". IEEE Transactions on Circuits and Systems II: Express Briefs (2022): http://www.scopus.com/inward/record.url?eid=2-s2.0-85126727267&partnerID=MN8TOARS.
    10.1109/TCSII.2022.3160191
  8. Vieira, J.; Roma, N.; Falcao, G.; Tomás, P.. "A Compute Cache System for Signal Processing Applications". Journal of Signal Processing Systems (2021): http://www.scopus.com/inward/record.url?eid=2-s2.0-85104420078&partnerID=MN8TOARS.
    10.1007/s11265-020-01626-y
  9. Porto, R.; Perleberg, M.; Afonso, V.; Zatt, B.; Roma, N.; Agostini, L.; Porto, M.. "Fast and energy-efficient approximate motion estimation architecture for real-time 4 K UHD processing". Journal of Real-Time Image Processing 18 3 (2021): 723-737. http://www.scopus.com/inward/record.url?eid=2-s2.0-85090565170&partnerID=MN8TOARS.
    10.1007/s11554-020-01014-6
  10. Neves, N.; Tomas, P.; Roma, N.. "Compiler-Assisted Data Streaming for Regular Code Structures". IEEE Transactions on Computers 70 3 (2021): 483-494. http://www.scopus.com/inward/record.url?eid=2-s2.0-85101481658&partnerID=MN8TOARS.
    10.1109/TC.2020.2990302
  11. Neves, N.; Tomás, P.; Roma, N.. "A Reconfigurable Posit Tensor Unit with Variable-Precision Arithmetic and Automatic Data Streaming". Journal of Signal Processing Systems 93 12 (2021): 1365-1385. http://www.scopus.com/inward/record.url?eid=2-s2.0-85116031795&partnerID=MN8TOARS.
    10.1007/s11265-021-01687-7
  12. Porto, R.; Correa, M.; Goebel, J.; Zatt, B.; Roma, N.; Agostini, L.; Porto, M.. "UHD 8K energy-quality scalable HEVC intra-prediction SAD unit hardware using optimized and configurable imprecise adders". Journal of Real-Time Image Processing 17 5 (2020): 1685-1701. http://www.scopus.com/inward/record.url?eid=2-s2.0-85076795792&partnerID=MN8TOARS.
    10.1007/s11554-019-00934-2
  13. Joao Guerreiro; Aleksandar Ilic; Nuno Roma; Pedro Tomas. "Modeling and Decoupling the GPU Power Consumption for Cross-Domain DVFS". IEEE Transactions on Parallel and Distributed Systems 30 11 (2019): 2494-2506. https://doi.org/10.1109/TPDS.2019.2917181.
    10.1109/TPDS.2019.2917181
  14. Rafael Marques; Luís Russo; Nuno Roma. "Flying tourist problem: Flight time and cost minimization in complex routes". Expert Systems with Applications 130 (2019): 172-187. https://doi.org/10.1016/j.eswa.2019.04.024.
    10.1016/j.eswa.2019.04.024
  15. Joao Guerreiro; Aleksandar Ilic; Nuno Roma; Pedro Tomas. "GPU Static Modeling Using PTX and Deep Structured Learning". IEEE Access 7 (2019): 159150-159161. https://doi.org/10.1109/ACCESS.2019.2951218.
    10.1109/ACCESS.2019.2951218
  16. Nuno Neves; Pedro Tomás; Nuno Roma. "Stream data prefetcher for the GPU memory interface". The Journal of Supercomputing 74 6 (2018): 2314-2328. https://doi.org/10.1007/s11227-018-2260-6.
    10.1007/s11227-018-2260-6
  17. Wang, B.; de Souza, D.F.; Alvarez-Mesa, M.; Chi, C.C.; Juurlink, B.; Ilic, A.; Roma, N.; Sousa, L.. "Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU". Signal Processing: Image Communication 62 (2018): 93-105. http://www.scopus.com/inward/record.url?eid=2-s2.0-85040084925&partnerID=MN8TOARS.
    10.1016/j.image.2017.12.009
  18. Guerreiro, J.; Ilic, A.; Roma, N.; Tomás, P.. "DVFS-aware application classification to improve GPGPUs energy efficiency". Parallel Computing (2018): http://www.scopus.com/inward/record.url?eid=2-s2.0-85043231354&partnerID=MN8TOARS.
    10.1016/j.parco.2018.02.001
  19. Roma, Nuno. "Efficient Parallelization of Perturbative Monte Carlo QM/MM Simulations in Heterogeneous Platforms". International Journal of High Performance Computing Applications (2017):
    10.1177/1094342016649420
  20. Sousa, L.; Roma, N.. "Special issue on real-time energy-aware circuits and systems for HEVC and for its 3D and SVC extensions". Journal of Real-Time Image Processing 13 1 (2017): http://www.scopus.com/inward/record.url?eid=2-s2.0-85017114439&partnerID=MN8TOARS.
    10.1007/s11554-017-0675-6
  21. Roma, N.; Nunez-Yanez, J.. "Editorial to special issue on energy efficient architectures for embedded systems". Eurasip Journal on Embedded Systems 2016 1 (2017): http://www.scopus.com/inward/record.url?eid=2-s2.0-84991574456&partnerID=MN8TOARS.
    10.1186/s13639-016-0054-6
  22. Neves, N.; Tomas, P.; Roma, N.. "Adaptive In-Cache Streaming for Efficient Data Management". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 7 (2017): 2130-2143. http://www.scopus.com/inward/record.url?eid=2-s2.0-85015641380&partnerID=MN8TOARS.
    10.1109/TVLSI.2017.2671405
  23. Wang, B.; de Souza, D.F.; Alvarez-Mesa, M.; Chi, C.C.; Juurlink, B.; Ilic, A.; Roma, N.; Sousa, L.. "GPU Parallelization of HEVC In-Loop Filters". International Journal of Parallel Programming (2017): 1-21. http://www.scopus.com/inward/record.url?eid=2-s2.0-85009290244&partnerID=MN8TOARS.
    10.1007/s10766-017-0488-z
  24. De Souza, D.F.; Ilic, A.; Roma, N.; Sousa, L.. "GHEVC: An Efficient HEVC Decoder for Graphics Processing Units". IEEE Transactions on Multimedia 19 3 (2017): 459-474. http://www.scopus.com/inward/record.url?eid=2-s2.0-85013434274&partnerID=MN8TOARS.
    10.1109/TMM.2016.2625261
  25. Feldt, J.; Miranda, S.; Pratas, F.; Roma, N.; Tomás, P.; Mata, R.A.. "Optimization and benchmarking of a perturbative Metropolis Monte Carlo quantum mechanics/molecular mechanics program". Journal of Chemical Physics 147 24 (2017): http://www.scopus.com/inward/record.url?eid=2-s2.0-85040074424&partnerID=MN8TOARS.
    10.1063/1.5009820
  26. David Nogueira; Pedro Tomas; Nuno Roma. "BowMapCL: Burrows-Wheeler Mapping on Multiple Heterogeneous Accelerators". IEEE/ACM Transactions on Computational Biology and Bioinformatics 13 5 (2016): 926-938. http://dx.doi.org/10.1109/TCBB.2015.2495149.
    10.1109/TCBB.2015.2495149
  27. Nuno Neves; Rui Neves; Nuno Horta; Pedro Tomás; Nuno Roma. "Multi-objective kernel mapping and scheduling for morphable many-core architectures". Expert Systems with Applications 45 (2016): 385-399. https://doi.org/10.1016%2Fj.eswa.2015.10.004.
    10.1016/j.eswa.2015.10.004
  28. Roma, Nuno. "Adaptive Scheduling Framework for Real-Time Video Encoding on Heterogeneous Systems". IEEE Transactions on Circuits and Systems for Video Technology (2015):
    10.1109/TCSVT.2015.2402893
  29. Ferreirinha, T.; Nunes, R.; Azevedo, L.; Soares, A.; Pratas, F.; Tomás, P.; Roma, N.. "Acceleration of stochastic seismic inversion in OpenCL-based heterogeneous platforms". Computers and Geosciences 78 (2015): 26-36. http://www.scopus.com/inward/record.url?eid=2-s2.0-84923006517&partnerID=MN8TOARS.
    10.1016/j.cageo.2015.02.005
  30. de Souza, D.F.; Ilic, A.; Roma, N.; Sousa, L.. "GPU-assisted HEVC intra decoder". Journal of Real-Time Image Processing (2015): http://www.scopus.com/inward/record.url?eid=2-s2.0-84936869496&partnerID=MN8TOARS.
    10.1007/s11554-015-0519-1
  31. Neves, N.; Mendes, H.; Chaves, R.J.; Tomás, P.; Roma, N.. "Morphable hundred-core heterogeneous architecture for energy-aware computation". IET Computers and Digital Techniques 9 1 (2015): 49-62. http://www.scopus.com/inward/record.url?eid=2-s2.0-84921038801&partnerID=MN8TOARS.
    10.1049/iet-cdt.2014.0078
  32. Ferreira, M.; Roma, N.; Russo, L.M.S.. "Cache-Oblivious parallel SIMD Viterbi decoding for sequence search in HMMER". BMC Bioinformatics 15 1 (2014): http://www.scopus.com/inward/record.url?eid=2-s2.0-84904541795&partnerID=MN8TOARS.
    10.1186/1471-2105-15-165
  33. Neves, N.; Sebastiao, N.; Matos, D.; Tomas, P.; Flores, P.; Roma, N.. "Multicore SIMD ASIP for Next-Generation Sequencing and Alignment Biochip Platforms". IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2014): http://www.scopus.com/inward/record.url?eid=2-s2.0-84904526089&partnerID=MN8TOARS.
    10.1109/TVLSI.2014.2333757
  34. Momcilovic, S.; Ilic, A.; Roma, N.; Sousa, L.. "Dynamic load balancing for real-time video encoding on heterogeneous CPU+GPU systems". IEEE Transactions on Multimedia 16 1 (2014): 108-121. http://www.scopus.com/inward/record.url?eid=2-s2.0-84890932461&partnerID=MN8TOARS.
    10.1109/TMM.2013.2284892
  35. Dias, T.; Roma, N.; Sousa, L.. "Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs". Eurasip Journal on Advances in Signal Processing 2014 1 (2014): 1-15. http://www.scopus.com/inward/record.url?eid=2-s2.0-84919926224&partnerID=MN8TOARS.
    10.1186/1687-6180-2014-108
  36. Sebastião, N.; Roma, N.; Flores, P.. "Configurable and scalable class of high performance hardware accelerators for simultaneous DNA sequence alignment". Concurrency Computation Practice and Experience 25 10 (2013): 1319-1339. http://www.scopus.com/inward/record.url?eid=2-s2.0-84879413445&partnerID=MN8TOARS.
    10.1002/cpe.2934
  37. Momcilovic, S.; Roma, N.; Sousa, L.. "Exploiting task and data parallelism for advanced video coding on hybrid CPU + GPU platforms". Journal of Real-Time Image Processing (2013): 1-17. http://www.scopus.com/inward/record.url?eid=2-s2.0-84878237692&partnerID=MN8TOARS.
    10.1007/s11554-013-0357-y
  38. Dias, T.; López, S.; Roma, N.; Sousa, L.. "Scalable unified transform architecture for advanced video coding embedded systems". International Journal of Parallel Programming 41 2 (2013): 236-260. http://www.scopus.com/inward/record.url?eid=2-s2.0-84879604020&partnerID=MN8TOARS.
    10.1007/s10766-012-0221-x
  39. Sebastião, N.; Roma, N.; Flores, P.. "Hardware accelerator architecture for simultaneous short-read DNA sequences alignment with enhanced traceback phase". Microprocessors and Microsystems 36 2 (2012): 96-109. http://www.scopus.com/inward/record.url?eid=2-s2.0-84857241193&partnerID=MN8TOARS.
    10.1016/j.micpro.2011.05.003
  40. Sebastião, N.; Roma, N.; Flores, P.. "Integrated hardware architecture for efficient computation of the n-Best Bio-sequence local alignments in embedded platforms". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 7 (2012): 1262-1275. http://www.scopus.com/inward/record.url?eid=2-s2.0-84862024420&partnerID=MN8TOARS.
    10.1109/TVLSI.2011.2157541
  41. Sebastião, N.; Encarnação, G.; Roma, N.. "Implementation and performance analysis of efficient index structures for DNA search algorithms in parallelplatforms". Concurrency Computation Practice and Experience (2012): http://www.scopus.com/inward/record.url?eid=2-s2.0-84871519655&partnerID=MN8TOARS.
    10.1002/cpe.2970
  42. Tiago Miguel Braga da Silva Dias; Svetislav Momcilovic; Nuno Roma; Leonel Sousa. "Video Coding Platforms for Mobile Multimedia Networks". 6 6 (2011): 24-26. https://scholar.tecnico.ulisboa.pt/records/EhlYIRIMjLw9_6DD5aBU117cCZCwJIPvaQ_u.
    Published
  43. Roma, N.; Sousa, L.. "A tutorial overview on the properties of the discrete cosine transform for encoded image and video processing". Signal Processing 91 11 (2011): 2443-2464. http://www.scopus.com/inward/record.url?eid=2-s2.0-79960173837&partnerID=MN8TOARS.
    10.1016/j.sigpro.2011.04.015
  44. Dias, T.; López, S.; Roma, N.; Sousa, L.. "A flexible architecture for the computation of direct and inverse transforms in H.264/AVC video codecs". IEEE Transactions on Consumer Electronics 57 2 (2011): 936-944. http://www.scopus.com/inward/record.url?eid=2-s2.0-79960929422&partnerID=MN8TOARS.
    10.1109/TCE.2011.5955243
  45. Dias, T.; Momcilovic, S.; Roma, N.; Sousa, L.. "Adaptive motion estimation processor for autonomous video devices". Eurasip Journal on Embedded Systems 2007 (2007): http://www.scopus.com/inward/record.url?eid=2-s2.0-34250851339&partnerID=MN8TOARS.
    10.1155/2007/57234
  46. Roma, N.; Sousa, L.. "Efficient hybrid DCT-domain algorithm for video spatial downscaling". Eurasip Journal on Advances in Signal Processing 2007 (2007): http://www.scopus.com/inward/record.url?eid=2-s2.0-36248999529&partnerID=MN8TOARS.
    10.1155/2007/57291
  47. Dias, T.; Roma, N.; Sousa, L.; Ribeiro, M.. "Reconfigurable architectures and processors for real-time video motion estimation". Journal of Real-Time Image Processing 2 4 (2007): 191-205. http://www.scopus.com/inward/record.url?eid=2-s2.0-36949007430&partnerID=MN8TOARS.
    10.1007/s11554-007-0049-6
  48. Roma, N.; Sousa, L.. "Automatic synthesis of motion estimation processors based on a new class of hardware architectures". Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 34 3 (2003): 277-290. http://www.scopus.com/inward/record.url?eid=2-s2.0-0038353880&partnerID=MN8TOARS.
    10.1023/A:1023204620405
  49. Roma, N.; Sousa, L.. "Fast transcoding architectures for insertion of non-regular shaped objects in the compressed DCT-domain". Signal Processing: Image Communication 18 8 SPEC. (2003): 659-683. http://www.scopus.com/inward/record.url?eid=2-s2.0-0042328300&partnerID=MN8TOARS.
    10.1016/S0923-5965(03)00058-4
  50. Roma, N.; Sousa, L.. "Efficient and configurable full-search block-matching processors". IEEE Transactions on Circuits and Systems for Video Technology 12 12 (2002): 1160-1167. http://www.scopus.com/inward/record.url?eid=2-s2.0-0036995762&partnerID=MN8TOARS.
    10.1109/TCSVT.2002.806818

Other

Other output
  1. Gpu-Based Parallelisation of a Versatile Video Coding Adaptive Loop Filter in Resource-Constrained Heterogeneous Embedded Platform. 2022. Saha, A.; Roma, N.; Chavarrías, M.; Dias, T.; Pescador, F.; Aranda, V.. http://www.scopus.com/inward/record.url?eid=2-s2.0-85176967811&partnerID=MN8TOARS.
    10.2139/ssrn.4178254
  2. Positnn: Training deep neural networks with mixed Low-precision posit. 2021. Raposo, G.; Tomás, P.; Roma, N.. http://www.scopus.com/inward/record.url?eid=2-s2.0-85107645599&partnerID=MN8TOARS.
  3. Positnn: Training deep neural networks with mixed Low-precision posit. 2021. Raposo, G.; Tomás, P.; Roma, N.. http://www.scopus.com/inward/record.url?eid=2-s2.0-85169283815&partnerID=MN8TOARS.
    10.48550/arxiv.2105.00053
Activities

Supervision

Thesis Title
Role 		Degree Subject (Type)
Institution / Organization
2023/02/01 - Current Compilation Abstraction and Hardware Adaptation for Specialized and General-Purpose Computing Unification
Supervisor
 Engenharia Electrotécnica e de Computadores (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2023/02/01 - Current 5D calorimetry at the HL-LHC: hard real-time embedded architectures for system testing and production
Supervisor
 Engenharia Electrotécnica e de Computadores (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2022/02/01 - Current Accelerating the ATLAS Trigger System with Graphical Processing Units
Co-supervisor
 Engenharia Física (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2019/08/29 - Current Processing-In-Memory for General-Purpose Applications: Improving Performance and Energy Efficiency with a Locality-Aware Architecture and Compiler
Co-supervisor
 Engenharia Eletrotécnica e de Computadores (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/03/01 - 2020/06/02 DVFS Modeling for Energy-Efficient GPU Computing
Co-supervisor of João Filipe Dias Guerreiro
 Engenharia Eletrotécnica e de Computadores (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016/09/01 - 2020/04/13 Exploração de Computação Aproximada no Projeto de Hardware Dedicado de Baixo Consumo para a Codificação de Vídeo em Dispositivos Móveis
Co-supervisor
 Programa de Pós-Graduação em Computação (PhD)
Universidade Federal de Pelotas, Brazil
2014/09/01 - 2019/01/08 Energy-Efficient Computing: Adaptive Structures and Data Management
Supervisor of Nuno Filipe Simões Santos Moraes Neves
 Engenharia Eletrotécnica e de Computadores (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2014/09/01 - 2018/07/10 GHEVC: An Efficient HEVC Decoder for Graphics Processing Units
Co-supervisor of Diego Felix de Souza
 Engenharia Eletrotécnica e de Computadores (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2012/09/01 - 2016/06/16 Heterogeneous multi-core parallel structures for biological sequences alignment
Supervisor of Nuno Carlos André Sebastião
 Engenharia Eletrotécnica e de Computadores (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2011/09/01 - 2015/06/22 High performance and scalable unified architectures for transform and quantization in H.264/AVC video codecs
Supervisor of Tiago Miguel Braga Da Silva Dias
 Engenharia Eletrotécnica e de Computadores (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
Distinctions

Award

2021 Técnico Outstanding Teaching Award
Universidade de Lisboa Instituto Superior Técnico, Portugal

Title

2018 ACM Senior Member
Association for Computing Machinery, United States
2016 Membro Sénior - Ordem dos Engenheiros
Ordem dos Engenheiros, Portugal
2013 IEEE Senior Member
IEEE, United States