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Ricardo Jorge Ferreira Nobre. Completed the Doutoramento in Engenharia Informática (PhD in Informatics Engineering) in 2017 by Universidade do Porto Faculdade de Engenharia, Mestrado in Engenharia Informática e de Computadores (MSc in Computer Science and Engineering) in 2011 by Universidade de Lisboa Instituto Superior Técnico Campus Taguspark and Licenciatura in Engenharia Informática e de Computadores (BSc in Computer Science and Engineering) in 2008 by Universidade de Lisboa Instituto Superior Técnico Campus Taguspark. Is Auxiliary Researcher in Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa. Published 5 articles in journals. Has 3 section(s) of books. Organized 4 event(s). Participated in 8 event(s). Has received 4 awards and/or honors. Participates and/or participated as Principal investigator in 2 project(s) and Researcher in 5 project(s). Works in the area(s) of Exact Sciences with emphasis on Computer and Information Sciences. In his curriculum Ciência Vitae the most frequent terms in the context of scientific, technological and artistic-cultural output are: compiler optimization; aspects-oriented programming; MATLAB; heterogeneous system; bioinformatics; energy-efficinecy; performance modeling; embedded system; GWAS; two- and three-way epistasis detection; performance evaluation; parallel processing; GPU.
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Identification

Personal identification

Full name
Ricardo Jorge Ferreira Nobre

Citation names

  • Nobre, Ricardo

Author identifiers

Ciência ID
C312-3BFB-C7C0
ORCID iD
0000-0003-1639-4545
Researcher Id
AAL-6558-2020
Scopus Author Id
55202982900

Email addresses

  • ricardo.nobre@inesc-id.pt (Professional)

Telephones

Telephone
  • 213100300 (Professional)

Addresses

  • Rua Alves Redol, 9 , 1000-029, Lisboa , Lisboa , Portugal (Professional)

Knowledge fields

  • Exact Sciences - Computer and Information Sciences

Languages

Language Speaking Reading Writing Listening Peer-review
English Advanced (C1) Advanced (C1) Intermediate (B1) Advanced (C1)
French Beginner (A1) Intermediate (B1) Beginner (A1) Beginner (A1)
Portuguese (Mother tongue)
Education
Degree Classification
2017
Concluded
 Engenharia Informática (PhD in Informatics Engineering) (Doutoramento)
Universidade do Porto Faculdade de Engenharia, Portugal
"Efficient target and application specific selection and ordering of compiler passes" (THESIS/DISSERTATION)
 Aprovado
2011
Concluded
 Engenharia Informática e de Computadores (MSc in Computer Science and Engineering) (Mestrado)
Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
 16
2008
Concluded
 Engenharia Informática e de Computadores (BSc in Computer Science and Engineering) (Licenciatura)
Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
 15
Affiliation

Science

Category
Host institution 		Employer
2022/02 - Current Auxiliary Researcher (Research) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2019/04 - 2021/12 Researcher (Research) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2011 - 2018 Researcher (Research) Instituto de Engenharia de Sistemas e Computadores Tecnologia e Ciência, Portugal
2008 - 2010 Researcher (Research) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Teaching in Higher Education

Category
Host institution 		Employer
2016 - 2018 Invited Assistant Professor (University Teacher) Universidade do Porto Faculdade de Engenharia, Portugal
Universidade do Porto Faculdade de Engenharia, Portugal
Projects

Grant

Designation Funders
2016 - 2017 Smart, Mobile, Intelligent and Large scale Sensing and analytics (TEC4Growth - RL SMILES )
NORTE-01-0145-FEDER-000020
Researcher
Fundação para a Ciência e a Tecnologia
Concluded
2010 - 2012 Rendering FPGAs to Multi-core Embedded Computing (REFLECT)
FP7-ICT under contract No. 248976.
Researcher
European Commission Seventh Framework Programme for Research and Technological Development Information and Communication Technologies
Concluded
2009 - 2010 Aspects and Compiler Optimizations for MATLAB System Development (AMADEUS)
PTDC/EIA/70271/2006
Researcher
Fundação para a Ciência e a Tecnologia
Concluded

Contract

Designation Funders
2022/02 - Current SparCity: An Optimization and Co-design Framework for Sparse Computation
Grant agreement ID: 956213
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 European Commission
Ongoing
2019/04 - 2021/12 High Performance and Energy-efficient Processing for Bioinformatics Applications in Emergent Heterogeneous Systems (HiPErBio)
PTDC/CCI-COM/31901/2017
Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded

Other

Designation Funders
2024/06 - Current BioAccel: Leveraging A64FX CPUs and A100 GPUs for High-Speed Bioinformatics
2024.14230.CPCA.A3
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Ongoing
2022/11/01 - 2023/11/01 Epistasis Detection on Heterogeneous AI-Enhanced Platforms
CPCA-IAC/AV/478750/2022
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia

Google Inc
Concluded
2023/03/01 - 2023/10/31 Epistasis Detection on Supercomputing Platforms
EHPC-BEN-2023B01-002
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Concluded
2008 - 2009 Compilation and Synthesis of Image Processing Algorithms in Matlab for FPGA-based Custom Vectors Units (VECTOR)
PTDC/EEA-ELC/71556/2006
Researcher
Fundação para a Ciência e a Tecnologia
Concluded
Outputs

Publications

Book chapter
  1. Gonçalves, Fernando; Petrov, Zlatko; de F. Coutinho, José Gabriel; Nane, Razvan; Sima, Vlad-Mihai; Cardoso, João M. P.; Werner, Stephan; et al. "LARA Experiments". In Compilation and Synthesis for Embedded Reconfigurable Systems, 135-179. Springer New York, 2013.
    10.1007/978-1-4614-4894-5_6
  2. Nobre, Ricardo; Cardoso, João M. P.; Olivier, Bryan; Nane, Razvan; Fitzpatrick, Liam; de F. Coutinho, José Gabriel; van Someren, Hans; et al. "Hardware/Software Compilation". In Compilation and Synthesis for Embedded Reconfigurable Systems, 105-134. Springer New York, 2013.
    10.1007/978-1-4614-4894-5_5
  3. Cardoso, João M. P.; de F. Coutinho, José Gabriel; Nane, Razvan; Sima, Vlad-Mihai; Olivier, Bryan; Carvalho, Tiago; Nobre, Ricardo; et al. "The REFLECT Design-Flow". In Compilation and Synthesis for Embedded Reconfigurable Systems, 13-34. Springer New York, 2013.
    10.1007/978-1-4614-4894-5_2
Conference abstract
  1. Coutinho, José G.F.; Cardoso, João M.P.; Carvalho, Tiago; Nobre, Ricardo; Bhattacharya, Sujit; Diniz, Pedro C.. "Deriving Resource Efficient Designs Using the REFLECT Aspect-Oriented Approach". Paper presented in 9th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Lost Angeles, 2013.
    10.1007/978-3-642-36812-7_29
Conference paper
  1. Nobre, Ricardo; Ilic, Aleksandar (ED15-73C2-57D1); Sergio Santander-Jiménez (4814-D336-C969); Sousa, Leonel (1212-9D42-1510). "IPU-EpiDet: Identifying Gene Interactions on Massively Parallel Graph-Based AI Accelerators". Paper presented in 38th International Parallel and Distributed Processing Symposium (IPDPS) [Ranked "A" in CORE2023] (Accepted), San Francisco, 2024.
    Accepted
  2. Nobre, Ricardo; Ilic, Aleksandar; Santander-Jiménez, Sergio; Sousa, Leonel. "Tensor-Accelerated Fourth-Order Epistasis Detection on GPUs". Paper presented in 51th International Conference on Parallel Processing (ICPP) [Ranked "A" in CORE2021], (Virtual) Bordeaux, 2022.
    10.1145/3545008.3545066
  3. Nobre, Ricardo; Ilic, Aleksandar (ED15-73C2-57D1); Sergio Santander-Jiménez (4814-D336-C969); Sousa, Leonel (1212-9D42-1510). "Fourth-Order Exhaustive Epistasis Detection for the xPU Era". Paper presented in 50th International Conference on Parallel Processing (ICPP) [Ranked "A" in CORE2021], (Virtual) Chicago, 2021.
    10.1145/3472456.3472509
  4. Nobre, Ricardo; Sergio Santander-Jiménez; Sousa, Leonel; Aleksandar Ilic. "Accelerating 3-way Epistasis Detection with CPU+GPU processing". Paper presented in 23rd Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), New Orleans, 2020.
    10.1007/978-3-030-63171-0_6
  5. Nobre, Ricardo; Aleksandar Ilic; Sergio Santander-Jiménez; Sousa, Leonel. "Exploring the Binary Precision Capabilities of Tensor Cores for Epistasis Detection". Paper presented in 34th International Parallel and Distributed Processing Symposium (IPDPS) [Ranked "A" in CORE2020], New Orleans, 2020.
    10.1109/IPDPS47924.2020.00043
  6. Nobre, Ricardo; Reis, Luís; Cardoso, João M.P.. "Fast Heuristic-Based GPU Compiler Sequence Specialization". Paper presented in Euro-Par 2018: Parallel Processing Workshops (HeteroPar), Turin, 2018.
    10.1007/978-3-030-10549-5_39
  7. Gadioli, Davide; Nobre, Ricardo; Pinto, Pedro; Vitali, Emanuele; Ashouri, Amir H.; Palermo, Gianluca; Cardoso, Joao; Silvano, Cristina. "SOCRATES — A seamless online compiler and system runtime autotuning framework for energy-aware applications". Paper presented in Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018.
    10.23919/date.2018.8342183
  8. Reis, Luís; Nobre, Ricardo; Cardoso, João M.P.. "Impact of Vectorization Over 16-bit Data-Types on GPUs". Paper presented in 9th Workshop and 7th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM), Manchester, 2018.
    10.1145/3183767.3183777
  9. Nobre, Ricardo; Reis, Luís; Bispo, João; Carvalho, Tiago; Cardoso, João M.P.; Cherubin, Stefano; Agosta, Giovanni. "Aspect-Driven Mixed-Precision Tuning Targeting GPUs". Paper presented in 9th Workshop and 7th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM), Manchester, 2018.
    10.1145/3183767.3183776
  10. Nobre, Ricardo; Reis, Luís; Cardoso, João M.P.. "Impact of Compiler Phase Ordering When Targeting GPUs". Paper presented in Euro-Par 2017: Parallel Processing Workshops (HeteroPar), Santiago de Compostela, 2017.
    10.1007/978-3-319-75178-8_35
  11. Silvano, Cristina; Agosta, Giovanni; Barbosa, Jorge; Bartolini, Andrea; Beccari, Andrea R.; Benini, Luca; Bispo, João; et al. "The ANTAREX tool flow for monitoring and autotuning energy efficient HPC systems". Paper presented in International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Pythagorion, 2017.
    10.1109/samos.2017.8344645
  12. Nobre, Ricardo; Martins, Luiz G. A.; Cardoso, João M. P.. "A graph-based iterative compiler pass selection and phase ordering approach". Paper presented in 17th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) [Ranked "A" in CORE2020], Santa Barbara, 2016.
    10.1145/2907950.2907959
  13. Nobre, Ricardo; Martins, Luiz G.A.; Cardoso, João M.P.. "Use of Previously Acquired Positioning of Optimizations for Phase Ordering Exploration". Paper presented in 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES) [Ranked "A" in CORE2020], St. Goar, 2015.
    10.1145/2764967.2764978
  14. Martins, Luiz G.A.; Nobre, Ricardo; Delbem, Alexandre C.B.; Marques, Eduardo; Cardoso, João M.P.. "A clustering-based approach for exploring sequences of compiler optimizations". Paper presented in IEEE Congress on Evolutionary Computation (CEC), Beijing, 2014.
    10.1109/cec.2014.6900634
  15. Martins, Luiz G.A.; Nobre, Ricardo; Cardoso, João M.P.; Delbem, Alexandre; Marques, Eduardo R.B.. "Exploration of compiler optimization sequences using clustering-based selection". Paper presented in SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems (LCTES) [Ranked "A" in CORE2020], Edinburgh, 2014.
    10.1145/2883614
  16. Nobre, Ricardo; Pinto, Pedro; Carvalho, Tiago; Cardoso, João M.P.; Diniz, Pedro C.. "On Expressing Strategies for Directive-Driven Multicore Programing Models". Paper presented in 5th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM), Vienna, 2014.
    10.1145/2556863.2556870
  17. Bispo. João; Pinto, Pedro; Nobre, Ricardo; Carvalho, Tiago; Cardoso, João M.P.; Diniz, Pedro C.. "The MATISSE MATLAB compiler". Paper presented in 11th IEEE International Conference on Industrial Informatics (INDIN), Bochum, 2013.
    10.1109/indin.2013.6622952
  18. Cardoso, João M.P.; Teixeira, João; Alves, José C.; Nobre, Ricardo; Diniz, Pedro C.; Coutinho, José G.F.; Luk, Wayne. "Specifying Compiler Strategies for FPGA-based Systems". Paper presented in 20th International Symposium on Field-Programmable Custom Computing Machines (FCCM) [Ranked "A" in CORE2020], Toronto, 2012.
    10.1109/fccm.2012.41
  19. Cardoso, João M.P.; Carvalho, Tiago; Coutinho, José G.F.; Luk, Wayne; Nobre, Ricardo; Diniz, Pedro C.; Petrov, Zlatko. "LARA: an aspect-oriented programming language for embedded systems". Paper presented in 11th annual international conference on Aspect-oriented Software Development (AOSD) [Ranked "A" in CORE2018], Potsdam, 2012.
    10.1145/2162049.2162071
  20. Coutinho, José G.F.; Carvalho, Tiago; Durand, Sergio; Cardoso, João M.P.; Nobre, Ricardo; Diniz, Pedro C.; Luk, Wayne. "Experiments with the LARA aspect-oriented approach". Paper presented in 11th annual international conference on Aspect-oriented Software Development (AOSD) — Demonstration Paper, Potsdam, 2012.
    10.1145/2162110.2162129
Journal article
  1. Graça, Miguel; Nobre, Ricardo; Sousa, Leonel; Ilic, Aleksandar. "Distributed transformer for high order epistasis detection in large-scale datasets". Scientific Reports [Ranked "Q1" in Scimago] 14 1 (2024):
    Published • 10.1038/s41598-024-65317-5
  2. Nobre, Ricardo; Aleksandar Ilic; Sergio Santander-Jiménez; Sousa, Leonel. "Retargeting Tensor Accelerators for Epistasis Detection". IEEE Transactions on Parallel and Distributed Systems [Ranked "Q1" in Scimago] (2021):
    10.1109/TPDS.2021.3060322
  3. Nobre, Ricardo; Carvalho, Tiago; Bispo, João; Cardoso, João M.P.. "Nonio — modular automatic compiler phase selection and ordering specialization framework for modern compilers". SoftwareX (2019):
    10.1016/j.softx.2019.100238
  4. Martins, Luiz G. A.; Nobre, Ricardo; Cardoso, João M. P.; Delbem, Alexandre C. B.; Marques, Eduardo. "Clustering-Based Selection for the Exploration of Compiler Optimization Sequences". ACM Transactions on Architecture and Code Optimization 13 1 (2016): 1-28.
    10.1145/2883614
  5. Cardoso, João M.P.; Carvalho, Tiago; Coutinho, José G.F.; Nobre, Ricardo; Nane, Razvan; Diniz, Pedro C.; Petrov, Zlatko; Luk, Wayne; Bertels, Koen. "Controlling a complete hardware synthesis toolchain with LARA aspects". Microprocessors and Microsystems (2013):
    10.1016/j.micpro.2013.06.001
  6. Cardoso, João M.P.; Fernandes, João M.; Monteiro, Miguel; Carvalho, Tiago; Nobre, Ricardo. "Enriching MATLAB with aspect-oriented features for developing embedded systems". Journal of Systems Architecture (2013):
    10.1016/j.sysarc.2013.04.003
Online resource
  1. Nobre, Ricardo. GitHub code repository [IPU-EpiDet]. 2023. https://github.com/hiperbio/IPU-EpiDet.
  2. Nobre, Ricardo. GitHub code repository [Epi4Tensor]. 2022. https://github.com/hiperbio/Epi4Tensor.
  3. Nobre, Ricardo. GitHub code repository [cuda-episdet]. 2021. https://github.com/hiperbio/cuda-episdet.
  4. Nobre, Ricardo. GitHub code repository [tensor-episdet]. 2021. https://github.com/hiperbio/tensor-episdet.
  5. Nobre, Ricardo. GitHub code repository [crossarch-episdet]. 2021. https://github.com/hiperbio/crossarch-episdet.
  6. Nobre, Ricardo. GitHub code repository [nonio]. 2019. https://github.com/specs-feup/nonio.

Other

Other output
  1. Improving OpenCL Performance by Specializing Compiler Phase Selection and Ordering. 2018. Nobre, Ricardo; Reis, Luís; Cardoso, João M.P.. https://arxiv.org/abs/1810.10496.
  2. Compiler Phase Ordering as an Orthogonal Approach for Reducing Energy Consumption. 2018. Nobre, Ricardo; Reis, Luís; Cardoso, João M.P.. https://arxiv.org/abs/1807.00638.
  3. Leveraging Type Knowledge for Efficient MATLAB to C Translation. In 15th Workshop on Compilers for Parallel Computing (CPC'10). 2010. Nobre, Ricardo; Cardoso, João M.P.; Diniz, Pedro C. (3D16-9F6F-D262). https://bit.ly/3ujOzXh.
Activities

Oral presentation

Presentation title Event name
Host (Event location)
2016/11/09 Suggestions about Submissions and Presentation of Reference Solution (Sugestões sobre as Soluções Submetidas e Apresentação da Solução de Referência) 1st Programming and Optimizing for Performance (POP'16) Competition (http://specs.fe.up.pt/pop16/)
2016/07/07 Compiler Phase Ordering as an Orthogonal Approach for Reducing Energy Consumption 19th Workshop on Compilers for Parallel Computing (CPC 2016)
(Valladolid, Spain)
2016/04/20 LARA Tutorial - Programming Strategies for Code Transformations and Optimizations HiPEAC Spring'16 Computing Systems Week (CSW)
(Porto, Portugal)
2014/04/13 A DSE example of using LARA for identifying compiler optimization sequences 10th Reconfigurable Systems Journeys (REC)
(Vilamoura, Portugal)
2013/09/02 Identifying Sequences of Optimizations for HW/SW Compilation (PhD Forum Session) 23rd international conference on field programmable logic and applications (FPL 2013)
(Porto, Portugal)

Event organisation

Event name
Type of event (Role) 		Institution / Organization
2021 - 2021 Organizing Committee (Virtual Chair) of the 27th International European Conference on Parallel and Distributed Computing (EuroPar 2021) (2021/08/30 - 2021/09/03)
Conference (Member of the Organising Committee)
 Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Universidade de Lisboa Instituto Superior Técnico, Portugal
2014 - 2014 Organizing Committee (Student Volunteer) of 10th International Symposium on Applied Reconfigurable Computing (ARC 2014) (2014/04/14 - 2014/04/16)
Symposium
 Universidade do Porto Faculdade de Engenharia, Portugal
2013 - 2013 Organizing Committee (Student Volunteer) of the 23rd International Conference on Field Programmable Logic and Applications (FPL 2013) (2013/09/02 - 2013/09/04)
Conference (Member of the Organising Committee)
 Universidade do Porto Faculdade de Engenharia, Portugal
2012 - 2012 Organizing Committee (Student Volunteer) of the REFLECT and 2PARMA Fall 2012 School — Programming Paradigms for Multi-Core Embedded Systems (2012/10/02 - 2012/10/05)
Other
 Universidade do Porto Faculdade de Engenharia, Portugal

Event participation

Activity description
Type of event 		Event name
Institution / Organization
2022/11/07 - Current Panelist at session on artificial intelligence and use of Google Cloud Platform as a research tool
Other
 Conversation with Researchers: Artificial Intelligence in the Cloud (FCT+Google event at LNEC)
2013/07/14 - 2013/07/14 Poster Presentation: "Identifying Sequences of Optimizations for HW/SW Compilation"
Other
 Ninth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2013)
2013/07/02 - 2013/07/04 Poster Presentation: "LARA-based Strategies for Source-to-Source Transformations Targeting Multicore Architectures"
Workshop
 Workshop on Research Projects Focusing on High Performance Computing (HPCW’13) / 23rd international conference on field programmable logic and applications (FPL 2013)
2013/01/21 - 2013/01/23 Poster Presentation: "Using LARA to Program Strategies for Targeting Hardware/Software Systems"
Conference
 8th International Conference on High-Performance and Embedded Architectures and Compilers (HIPEAC 2013)
2012/03/16 - 2012/03/16 Poster Presentation: "Design Space Exploration for FPGA-based Systems using LARA".
Conference
 Design, Automation, and Test in Europe (DATE 2012)
2012/03/16 - 2012/03/16 Poster Presentation: "A Domain-Specific Aspect Language for MATLAB and its Strategic Programming Weaver"
Conference
 Design, Automation, and Test in Europe (DATE 2012)
2012/01/25 - 2012/01/25 Poster Presentation: "LARA: An Aspect-oriented Approach for Developing and Designing Embedded Systems"
Conference
 7th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC 2012)
2011/07/03 - 2011/07/09 Poster Presentation: "MATLAB to C Conversion Targeting Embedded Systems"
Other
 4th Summer School on Generative and Transformational Techniques in Software Engineering (GTTSE 2011)

Jury of academic degree

Topic
Role 		Candidate name (Type of degree)
Institution / Organization
2021/12/20 Efficient execution of Java programs on GPU
(Thesis) Main arguer
 Gonçalo Medeiros São Pedro Raposo (Master)
Universidade do Minho Escola de Engenharia, Portugal
2021/10/14 An Exploration of FPGAs as Accelerators for Graph Analysis via High-Level Synthesis
(Thesis) Main arguer
 Pedro Filipe Vilhena de Campos Oliveira e Silva (Master)
Universidade do Porto Faculdade de Engenharia, Portugal
2021/10/13 Parallelization of the ADI Method Exploring Vector Computing in GPUs
(Thesis) Main arguer
 Filipe Pereira da Silva (Master)
Universidade do Minho Escola de Engenharia, Portugal
2020/10/13 Recommendation Engine for Parallel Loops
(Thesis) Main arguer
 José Luis Oliveira da Cunha (Master)
Universidade do Porto Faculdade de Engenharia, Portugal
2019/07/12 Acceleration of Applications with FPGA-Based Computing Machines: New DSL
(Thesis) Main arguer
 Daniel Alexandre Pimenta Lopes Fernandes (Master)
Universidade do Porto Faculdade de Engenharia, Portugal
2019/07/12 On Making Feasible Smartphone-Based Human Activity Recognition
(Thesis) Main arguer
 Francisco Miguel Lamares Martins Barbosa (Master)
Universidade do Porto Faculdade de Engenharia, Portugal
2019/07/12 Aspect-Oriented Programming for Javascript Using the LARA Language
(Thesis) Main arguer
 Ricardo Sá Loureiro Ferreira da Silva (Master)
Universidade do Porto Faculdade de Engenharia, Portugal

Committee member

Activity description
Role 		Institution / Organization
2023 - 2023 Program Committee of the 21th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar 2023)
Member
 Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2022 - 2022 Program Committee of the 20th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar 2022)
Member
 Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Course / Discipline taught

Academic session Degree Subject (Type) Institution / Organization
2018 - 2018 CPAR (Computação Paralela / Parallel Computing) — Theoretical + Practical Classes Engenharia Informática e Computação (Mestrado integrado) Universidade do Porto Faculdade de Engenharia, Portugal
2016 - 2018 LCOM (Laboratórios de Computadores / Computer Laboratory) — Practical Classes Engenharia Informática e Computação (Mestrado integrado) Universidade do Porto Faculdade de Engenharia, Portugal
2016 - 2018 COMP (Compiladores / Compilers) — Practical Classes Engenharia Informática e Computação (Mestrado integrado) Universidade do Porto Faculdade de Engenharia, Portugal

Interview (newspaper / magazine)

Activity description Newspaper / Forum
2023/11 INESC ID Interview with Aleksandar Ilic and Ricardo Nobre from the HPCAS Research Group (https://www.inesc-id.pt/inesc-id-interview-with-aleksandar-ilic-and-ricardo-nobre-from-the-hpcas-research-group/) INESC-ID News
2023/08 INESC-ID Achieves 9x Acceleration for Epistasis Disease Detection using oneAPI Tools and Intel Hardware (https://www.intel.com/content/www/us/en/developer/articles/casestudy/ inesc-id-9x-acceleration-for-disease-detection-app.html) Intel Tech.Decoded

Interview (tv / radio show)

Program Topic
2023/09 - 2023/09 Intel Code Together Accelerating Epistasis Detection - How oneAPI Supports Genetics Researchers (https://codetogether.podbean.com/e/accelerating-epistasis-detection-how-oneapi-supports-genetics-research/)
2021/06 - 2021/06 Intel Code Together Advancing Bioinformatics with Modern Hardware, HPC Compute + Software (https://www.oneapi.io/media-x/advancing-bioinformatics-with-modern-hardware-hpc-compute-software/)

Other jury / evaluation

Activity description Institution / Organization
2023 - 2023 Reviewer for 26th Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP 2023)
2023 - 2023 Reviewer for 34rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2023)
2023 - 2023 Reviewer for 33rd International Conference on Field-Programmable Logic and Applications (FPL 2023)
2023 - 2023 Reviewer for 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2023)
2023 - 2023 Reviewer for Subreviewer Wiley Concurrency and Computation: Practice and Experience
2023 - 2023 Reviewer for 52nd International Conference on Parallel Processing (ICPP 2023)
2022 - 2022 Reviewer for 33rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2022)
2022 - 2022 Reviewer for 25th Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP 2022)
2022 - 2022 Reviewer for 36th IEEE Workshop on Signal Processing Systems (IEEE SiPS 2022)
2022 - 2022 Reviewer for 14th International Conference on Parallel Processing and Applied Mathematics (PPAM 2022)
2022 - 2022 Reviewer for 8th International Conference on Multimedia Big Data (BigMM 2022)
2021 - 2021 Reviewer for IEEE Transactions on Parallel and Distributed Systems
2021 - 2021 Subreviewer for 18th International Conference on High Performance Computing & Simulation (HPCS 2020)
2021 - 2021 Subreviewer Wiley Concurrency and Computation: Practice and Experience
2021 - 2021 Subreviewer for 24rd Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP 2021)
2021 - 2021 Subreviewer for 27th International European Conference on Parallel and Distributed Computing (Euro-Par 2021)
2021 - 2021 Reviewer for 23rd IEEE International Conference on Cluster Computing (CLUSTER 2021)
2021 - 2021 Subreviewer for IEEE Transactions on Green Communications and Networking
2021 - 2021 Subreviewer for 55th Asilomar Conference on Signals, Systems, and Computers
2021 - 2021 Reviewer for 19th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2021)
2021 - 2021 Reviewer for 12th International Symposium on Parallel Architectures, Algorithms and Programming (PAAP’21)
2020 - 2020 Subreviewer for 23rd Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP 2020)
2020 - 2020 Subreviewer for 26th International European Conference on Parallel and Distributed Computing (Euro-Par 2020)
2020 - 2020 Reviewer for Elsevier Journal of Systems Architecture: Embedded Software Design
2020 - 2020 Reviewer for IEEE Transactions on Computers
2020 - 2020 Subreviewer for Design, Automation and Test in Europe Conference (DATE 2021)
2020 - 2020 Reviewer for 22nd IEEE International Conference on Cluster Computing (CLUSTER 2020)
2020 - 2020 Subreviewer for 26th International European Conference on Parallel and Distributed Computing (Euro-Par 2020 Workshops / HeteroPar)
2020 - 2020 Subreviewer for 34th ACM International Conference on Supercomputing (ICS 2020)
2019 - 2019 Subreviewer for 13th International Conference on Parallel Processing and Applied Mathematics (PPAM 2019)
2019 - 2019 Subreviewer for 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2020)
2019 - 2019 Subreviewer for 25th International European Conference on Parallel and Distributed Computing (Euro-Par 2019 Workshops / HeteroPar)
Distinctions

Award

2021 One of the top five winners for the oneAPI Great Cross-Architecture Challenge. Awarded by Intel Corporation, in collaboration with the European Organization for Nuclear Research (CERN) and Argonne National Laboratory.
2020 Best paper award nominee: "Exploring the Binary Precision Capabilities of Tensor Cores for Epistasis Detection". IEEE 34th International Parallel and Distributed Processing Symposium (IPDPS 2020) [Ranked "A" in CORE2020]
2012 HiPEAC Paper Award: "Specifying Compiler Strategies for FPGA-based Systems". IEEE 20th International Symposium on Field-Programmable Custom Computing Machines (FCCM 2012) [Ranked "A" in CORE2020]
2012 Student Poster Award: "MATLAB to C Conversion Targeting Embedded Computing Systems". 7th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC 2012)