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Paulo Flores received the Ph.D., M.Sc., and B.Sc. (5 years) degrees in Electrical and Computer Engineering from the Instituto Superior Técnico (IST), University of Lisbon (ULisboa), Portugal, in 2001, 1993, and 1989, respectively. Since 1990, he has been teaching at Instituto Superior Técnico, where he is currently an Associate Professor in the Electrical and Computer Engineering Department (ECE Dept). Since 1988 he has also been with Instituto de Engenharia de Sistemas e Computadores, Research and Development in Lisbon (INESC-ID), where he is currently a Senior Researcher in the High-Performance Computing Architectures and Systems (HPCAS) group. Paulo Flores has contributed with more than 70 research papers to peer-review journals and international conferences, and was the adviser of 25 Master's students and 2 PhDs. He was the leader, as Principal Investigator or Coordinator, in 6 research projects (3 of them funded by FCT: Multicon, ParSat, and QCell), and, as a researcher, he was involved in more than 15 national projects and 8 international projects. He holds one national patent resulting from his research work. He has been also a regular reviewer of technical papers in some major conferences of Electronic Design Automation and Circuits and Systems (DATE, DAC, ISCAS, DCIS, etc) and journals, mostly from IEEE (TCAD, IEEE-DT, TCAS, etc). Was editor of the special issue "Fault-Tolerant Architectures and Applications for Embedded and Reconfigurable Systems-on-a-Chip" on MDPI Electronics Journal and the special issue "Algorithms in Reconfigurable Computing" on MDPI Algorithms Journal. Paulo Flores is a Senior Member of IEEE Circuit and Systems Society and his major research interests are in the area of Embedded systems design; Reconfigurable computation and architectures (FPGAs); Optimization of hardware/software using satisfiability models (SAT); Algorithms and Electric Design Automation (EDA). Paulo Flores has been also involved in the creation and management of two technological strat-ups. He was a founding partner of the start-up Iknow, an Information Technology Consulting company founded in 2001. And in 2014 become part of the management team, as non-executive administrator, of Coreworks, a Semiconductor Intellectual Property company providing solutions for multiple standards and multimedia platforms developing reconfigurable hardware accelerators implemented in FPGAs and VLSI technologies.
Read full resume ↓
Identification

Personal identification

Full name
Paulo Flores

Citation names

  • Flores, Paulo

Author identifiers

Ciência ID
BF1D-DEA4-6418
ORCID iD
0000-0003-2970-3589
Google Scholar ID
usmU1KIAAAAJ
Researcher Id
C-2374-2008
Scopus Author Id
56357901100

Knowledge fields

  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Computer Hardware and Architecture
  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Electrical and Electronic Engineering
  • Exact Sciences - Computer and Information Sciences - Computer Sciences

Languages

Language Speaking Reading Writing Listening Peer-review
Portuguese (Mother tongue)
English Advanced (C1) Advanced (C1) Advanced (C1) Advanced (C1) Advanced (C1)
French Beginner (A1) Beginner (A1) Beginner (A1) Beginner (A1)
Spanish; Castilian Beginner (A1) Beginner (A1) Beginner (A1)
Education
Degree Classification
2001/12
Concluded
 Engenharia Electrotécnica e de Computadores (Doutoramento)
Major in Electrical and Computer Engineer
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Models and Algorithms for Optimization Problems in Digital Circuits Testing" (THESIS/DISSERTATION)
 Aprovado por unanimidade
1993/07
Concluded
 Engenharia Electrotécnica e de Computadores (Mestrado)
Major in Electrical and Computer Engineer
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Especificação funcional de sistemas electrónicos digitais em ambiente de síntese" (THESIS/DISSERTATION)
 Muito Bom por unanimidade (pre-belonha)
1989/06
Concluded
 Engenharia Electrotécnica e de Computadores (Licenciatura)
Major in Electrical and Computer Engineer
Universidade de Lisboa Instituto Superior Técnico, Portugal
"-" (THESIS/DISSERTATION)
 Average grade 16 points out of 20.
Affiliation

Science

Category
Host institution 		Employer
2000 - Current Principal Investigator (Research) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
1989 - 1999 Researcher (Research) Instituto de Engenharia de Sistemas e Computadores, Portugal

Teaching in Higher Education

Category
Host institution 		Employer
2020/11 - Current Associate Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
2021 - 2022 Invited Associate Professor (University Teacher) Academia da Força Aérea, Portugal
Academia da Força Aérea, Portugal
2018 - 2020 Invited Assistant Professor (University Teacher) Academia da Força Aérea, Portugal
Academia da Força Aérea, Portugal
2001 - 2020 Assistant Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal
1993/07 - 2001/10 Assistant (University Teacher) Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal
Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal
1990/01 - 1993/06 Trainee Assistant (University Teacher) Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal

Positions / Appointments

Category
Host institution 		Employer
2018 - 2019 Conselho geral ou orgão correspondente Universidade de Lisboa, Portugal
Projects

Grant

Designation Funders
2012/03 - 2015/02 CerVANTES: Co-VAlidatioN Tool for Embedded Systems
Provided by PTCRIS: 122756
122756
Researcher
Fundação para a Ciência e a Tecnologia, I.P.
2013/04 - 2014/09 QCell - Configurable Logic Block Cell for Quaternary FPGAs
128620
Provided by PTCRIS: 128620
EXPL/EEI-ELC/1016/2012
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia, I.P.

Fundação para a Ciência e a Tecnologia
Concluded
2011/01 - 2013/12 HELIX: Heterogeneous Multi-Core Architecture for Biological Sequence Analysis
Provided by PTCRIS: 113999
113999
Researcher
Fundação para a Ciência e a Tecnologia, I.P.
2010/04 - 2013/10 ParSat - Parallel Satisfiability Algorithms and its Applications
103532
Provided by PTCRIS: 103532
Principal investigator
Fundação para a Ciência e a Tecnologia, I.P.
2009/01 - 2012/07 Multicon - Architectural Optimization of DSP Systems with Multiple Constants Multiplications
70025
Provided by PTCRIS: 70025
Principal investigator
Fundação para a Ciência e a Tecnologia, I.P.
2005/01 - 2008/11 AMEP: Adaptive H.264/AVC Motion Estimation Processor for Mobile and Battery Supplied Devices
Provided by PTCRIS: 60765
60765
Researcher
Fundação para a Ciência e a Tecnologia, I.P.
2005/01 - 2008/06 PowerPlan - Electronic Systems Power Planning
Provided by PTCRIS: 61528
61528
Researcher
Fundação para a Ciência e a Tecnologia, I.P.

Contract

Designation Funders
2023/01/01 - Current NEUROPULS - NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS
101070238
Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 European Commission
Ongoing

Other

Designation Funders
2021/09/01 - 2023/12/31 Towards Approximate Edge Computing for Machine Learning & Digital Signal, Image and Video Processing
2019.00172.CBM
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Ongoing
2008 - 2011 Sideworks - Acelerador em hardware para alinhamento de múltiplas sequências biológicas
24781
Research Fellow
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Agência Nacional de Inovação SA
Concluded
Outputs

Publications

Book
  1. Aksoy, L.; Da Costa, E.; Flores, P.; Monteiro, J.. Multiplierless design of linear DSP transforms. 2012.
    10.1007/978-3-642-32770-4_5
  2. Lazzari, C.; Fernandes, J.; Flores, P.; Monteiro, J.. An efficient low power multiple-value look-up table targeting quaternary FPGAs. 2011.
    10.1007/978-3-642-17752-1-9
  3. Morgado, P.M.; Flores, P.F.; Monteiro, J.C.; Silveira, L.M.. Generating worst-case stimuli for accurate power grid analysis. 2009.
    10.1007/978-3-540-95948-9_25
Conference paper
  1. Liacha, A.; Oudjida, A.K.; Ferguene, F.; Monteiro, J.; Flores, P.. "A variable RADIX-2ralgorithm for single constant multiplication". 2017.
    10.1109/NEWCAS.2017.8010156
  2. Flores, Paulo. "A novel method for the approximation of multiplierless constant matrix vector multiplication". 2015.
    10.1109/EUC.2015.27
  3. Flores, Paulo. "Approximation of multiple constant multiplications using minimum look-up tables on FPGA". 2015.
    10.1109/ISCAS.2015.7169289
  4. Flores, Paulo. "Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA". 2014.
    10.1109/ICCD.2014.6974660
  5. Flores, Paulo. "Optimized ASIP architecture for compressed BWT-Indexed Search in bioinformatics applications". 2014.
    10.1109/HPCSim.2014.6903731
  6. Flores, Paulo. "ECHO: A novel method for the multiplierless design of constant array vector multiplication". 2014.
    10.1109/ISCAS.2014.6865420
  7. Aksoy, L.; Flores, P.; Monteiro, J.; Flores, Paulo. "Optimization of design complexity in time-multiplexed constant multiplications". 2014.
    10.7873/DATE2014.313
  8. Aksoy, L.; Flores, P.; Monteiro, J.. "SIREN: A depth-first search algorithm for the filter design optimization problem". 2013.
    10.1145/2483028.2483087
  9. Marques, R.; Guerra E Silva, L.; Flores, P.; Silveira, L.M.. "Improving SAT solver efficiency using a multi-core approach". 2013.
  10. Aksoy, L.; Costa, E.; Flores, P.; Monteiro, J.. "Exploration of tradeoffs in the design of integer cosine transforms for image compression". 2013.
  11. Aksoy, L.; Flores, P.; Monteiro, J.. "Towards the least complex time-multiplexed constant multiplication". 2013.
    10.1109/VLSI-SoC.2013.6673302
  12. Brito, D.; Fernandes, J.; Flores, P.; Monteiro, J.. "Standard CMOS voltage-mode QLUT using a clock boosting technique". 2013.
    10.1109/NEWCAS.2013.6573573
  13. Neves, N.; Sebastiao, N.; Patricio, A.; Matos, D.; Tomas, P.; Flores, P.; Roma, N.. "BioBlaze: Multi-core SIMD ASIP for DNA sequence alignment". 2013.
    10.1109/ASAP.2013.6567581
  14. Brito, D.; Fernandes, J.; Flores, P.; Monteiro, J.. "Design and characterization of a QLUT in a standard CMOS process". 2012.
    10.1109/ICECS.2012.6463744
  15. Aksoy, L.; Lazzari, C.; Costa, E.; Flores, P.; Monteiro, J.. "Optimization of area in digit-serial multiple constant multiplications at gate-level". 2011.
    10.1109/ISCAS.2011.5938171
  16. Aksoy, L.; Costa, E.; Flores, P.; Monteiro, J.. "Design of low-power multiple constant multiplications using low-complexity minimum depth operations". 2011.
    10.1145/1973009.1973026
  17. Aksoy, L.; Lazzari, C.; Costa, E.; Flores, P.; Monteiro, J.. "Efficient shift-adds design of digit-serial multiple constant multiplications". 2011.
    10.1145/1973009.1973023
  18. Aksoy, L.; Costa, E.; Flores, P.; Monteiro, J.. "A hybrid algorithm for the optimization of area and delay in linear DSP transforms". 2011.
    10.1109/VLSISoC.2011.6081637
  19. Aksoy, L.; Costa, E.; Flores, P.; Monteiro, J.. "Optimization of gate-level area in high throughput multiple constant multiplications". 2011.
    10.1109/ECCTD.2011.6043602
  20. Sebastião, N.; Dias, T.; Roma, N.; Flores, P.. "Integrated accelerator architecture for DNA sequences alignment with enhanced traceback phase". 2010.
    10.1109/HPCS.2010.5547154
  21. Lazzari, C.; Flores, P.; Monteiro, J.; Carro, L.. "Voltage-mode quaternary FPGAs: An evaluation of interconnections". 2010.
    10.1109/ISCAS.2010.5537423
  22. Aksoy, L.; Costa, E.; Flores, P.; Monteiro, J.. "Optimization of area and delay at gate-level in Multiple Constant Multiplications". 2010.
    10.1109/DSD.2010.32
  23. Jaccottet, D.; Costa, E.; Aksoy, L.; Flores, P.; Monteiro, J.. "Design of low-complexity and high-speed digital finite impulse response filters". 2010.
    10.1109/VLSISOC.2010.5642676
  24. Lazzari, C.; Flores, P.; Monteiro, J.C.. "Power and delay comparison of binary and quaternary arithmetic circuits". 2009.
    10.1109/ICSCS.2009.5412586
  25. Aksoy, L.; Costa, E.; Flores, P.; Monteiro, J.. "Minimum number of operations under a general number representation for digital filter synthesis". 2008.
    10.1109/ECCTD.2007.4529584
  26. Sebastião, N.; Dias, T.; Roma, N.; Flores, P.; Sousa, L.. "Application specific programmable IP core for motion estimation: Technology comparison targeting efficient embedded co-processing units". 2008.
    10.1109/DSD.2008.66
  27. Daitx, F.F.; Rosa, V.S.; Costa, E.; Flores, P.; Bampi, S.. "VHDL generation of optimized FIR filters". 2008.
    10.1109/ICSCS.2008.4746944
  28. Aksoy, L.; Gunes, E.O.; Flores, P.. "An exact breadth-first search algorithm for the multiple constant multiplications problem". 2008.
    10.1109/NORCHP.2008.4738280
  29. Morgado, P.M.; Flores, P.F.; Silveira, L.M.. "Generating realistic stimuli for accurate power grid analysis". 2007.
    10.1109/ISVLSI.2007.47
  30. Aksoy, L.; Costa, E.; Flores, P.; Monteiro, J.. "Optimization of area in digital FIR filters using gate-level metrics". 2007.
    10.1109/DAC.2007.375200
  31. Aksoy, L.; Gunes, E.O.; Costa, E.; Flores, P.; Monteiro, J.. "Effect of number representation on the achievable minimum number of operations in multiple constant multiplications". 2007.
    10.1109/SIPS.2007.4387585
  32. Aksoy, L.; Costa, E.; Flores, P.; Monteiro, J.. "Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming". 2006.
    10.1145/1146909.1147079
  33. Aksoy, L.; Costa, E.; Flores, P.; Monteiro, J.. "ASSUMEs: Heuristic algorithms for optimization of area and delay in digital filter synthesis". 2006.
    10.1109/ICECS.2006.379897
  34. Flores, P.; Monteiro, J.; Costa, E.. "An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications". 2005.
    10.1109/ICCAD.2005.1560032
  35. Da Costa, E.; Flores, P.; Monteiro, J.. "Maximal sharing of partial terms in MCM under minimal signed digit representation". 2005.
    10.1109/ECCTD.2005.1523033
Journal article
  1. Abreu, Brunno Alves; Mema, Albi; Thomann, Simon; Paim, Guilherme; Flores, Paulo; Bampi, Sergio; Amrouch, Hussam. Corresponding author: Abreu, Brunno Alves. "Compact CMOS-Compatible Majority Gate using Body Biasing in FDSOI Technology". IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2023): 1-1. http://dx.doi.org/10.1109/jetcas.2023.3243150.
    Accepted • 10.1109/jetcas.2023.3243150
  2. Arbeletche, Yuri; Paim, Guilherme; Abreu, Brunno; Almeida, Sergio; Costa, Eduardo; Flores, Paulo; Bampi, Sergio. "MAxPy: A Framework for Bridging Approximate Computing Circuits to its Applications". IEEE Transactions on Circuits and Systems II: Express Briefs (2023): 1-1. http://dx.doi.org/10.1109/tcsii.2023.3240897.
    Accepted • 10.1109/tcsii.2023.3240897
  3. Liacha, Ahmed; Oudjida, Abdelkrim K.; Bakiri, Mohammed; Monteiro, José; Flores, Paulo. "Radix-2^r recoding with common subexpression elimination for multiple constant multiplication". IET Circuits, Devices & Systems 14 7 (2020): 990-994. http://dx.doi.org/10.1049/iet-cds.2020.0213.
    Open access • 10.1049/iet-cds.2020.0213
  4. Flores, Paulo. "A novel method for the approximation of multiplierless constant matrix vector multiplication". EURASIP Journal on Embedded Systems (2016):
    10.1186/s13639-016-0033-y
  5. Flores, Paulo. "Multicore SIMD ASIP for next-generation sequencing and alignment biochip platforms". IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI) (2015):
    10.1109/TVLSI.2014.2333757
  6. Flores, Paulo. "Quaternary logic look-up table in standard CMOS". IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI) (2015):
    10.1109/TVLSI.2014.2308302
  7. Flores, Paulo. "Exact and approximate algorithms for the filter design optimization problem". IEEE Transactions on Signal Processing (2015):
    10.1109/TSP.2014.2366713
  8. Flores, Paulo. "Multiplierless design of folded DSP blocks". ACM Transactions on Design Automation of Electronic Systems (TODAES) (2014):
    10.1145/2663343
  9. Flores, Paulo. "A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures". Journal of Circuits, Systems, and Signal Processing (2014):
    10.1007/s00034-013-9727-8
  10. Sebastião, N.; Roma, N.; Flores, P.. "Configurable and scalable class of high performance hardware accelerators for simultaneous DNA sequence alignment". Concurrency Computation Practice and Experience 25 10 (2013): 1319-1339. http://www.scopus.com/inward/record.url?eid=2-s2.0-84879413445&partnerID=MN8TOARS.
    10.1002/cpe.2934
  11. Aksoy, L.; Lazzari, C.; Costa, E.; Flores, P.; Monteiro, J.. "Design of digit-serial FIR filters: Algorithms, architectures, and a CAD tool". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 3 (2013): 498-511. http://www.scopus.com/inward/record.url?eid=2-s2.0-84874646348&partnerID=MN8TOARS.
    10.1109/TVLSI.2012.2188917
  12. Aksoy, L.; Costa, E.; Flores, P.; Monteiro, J.. "Multiple tunable constant multiplications: Algorithms and applications". IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD (2012): 473-479. http://www.scopus.com/inward/record.url?eid=2-s2.0-84872329302&partnerID=MN8TOARS.
  13. Aksoy, L.; Lazzari, C.; Costa, E.; Flores, P.; Monteiro, J.. "High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications". Integration, the VLSI Journal 45 3 (2012): 294-306. http://www.scopus.com/inward/record.url?eid=2-s2.0-84860516076&partnerID=MN8TOARS.
    10.1016/j.vlsi.2011.11.008
  14. Aksoy, L.; Costa, E.; Flores, P.; Monteiro, J.. "Design of low-complexity digital finite impulse response filters on FPGAs". Proceedings -Design, Automation and Test in Europe, DATE (2012): 1197-1202. http://www.scopus.com/inward/record.url?eid=2-s2.0-84862067237&partnerID=MN8TOARS.
  15. Sebastião, N.; Roma, N.; Flores, P.. "Hardware accelerator architecture for simultaneous short-read DNA sequences alignment with enhanced traceback phase". Microprocessors and Microsystems 36 2 (2012): 96-109. http://www.scopus.com/inward/record.url?eid=2-s2.0-84857241193&partnerID=MN8TOARS.
    10.1016/j.micpro.2011.05.003
  16. Sebastião, N.; Roma, N.; Flores, P.. "Integrated hardware architecture for efficient computation of the n-Best Bio-sequence local alignments in embedded platforms". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 7 (2012): 1262-1275. http://www.scopus.com/inward/record.url?eid=2-s2.0-84862024420&partnerID=MN8TOARS.
    10.1109/TVLSI.2011.2157541
  17. Aksoy, L.; Costa, E.; Flores, P.; Monteiro, J.. "Optimization algorithms for the multiplierless realization of linear transforms". ACM Transactions on Design Automation of Electronic Systems 17 1 (2012): http://www.scopus.com/inward/record.url?eid=2-s2.0-84857851929&partnerID=MN8TOARS.
    10.1145/2071356.2071359
  18. Aksoy, L.; Costa, E.; Flores, P.; Monteiro, J.. "Finding the optimal tradeoff between area and delay in multiple constant multiplications". Microprocessors and Microsystems 35 8 (2011): 729-741. http://www.scopus.com/inward/record.url?eid=2-s2.0-81855225340&partnerID=MN8TOARS.
    10.1016/j.micpro.2011.08.009
  19. Lazzari, C.; Fernandes, J.; Flores, P.; Monteiro, J.. "Low power Multiple-value voltage-mode look-Up table for quaternary field programmable gate arrays". Journal of Low Power Electronics 7 2 (2011): 294-301. http://www.scopus.com/inward/record.url?eid=2-s2.0-84856970656&partnerID=MN8TOARS.
    10.1166/jolpe.2011.1138
  20. Aksoy, L.; Günes, E.O.; Flores, P.. "Search algorithms for the multiple constant multiplications problem: Exact and approximate". Microprocessors and Microsystems 34 5 (2010): 151-162. http://www.scopus.com/inward/record.url?eid=2-s2.0-77955182001&partnerID=MN8TOARS.
    10.1016/j.micpro.2009.10.001
  21. Lazzari, C.; Flores, P.; Monteiro, J.; Carro, L.. "A new quaternary FPGA based on a voltage-mode multi-valued circuit". Proceedings -Design, Automation and Test in Europe, DATE (2010): 1797-1802. http://www.scopus.com/inward/record.url?eid=2-s2.0-77953092496&partnerID=MN8TOARS.
  22. Aksoy, L.; Gunes, E.O.; Flores, P.. "Optimization of area under a delay constraint in multiple constant multiplications". Proceedings of the 13th WSEAS International Conference on Circuits - Held as part of the 13th WSEAS CSCC Multiconference (2009): 81-86. http://www.scopus.com/inward/record.url?eid=2-s2.0-74549115772&partnerID=MN8TOARS.
  23. Morgado, P.M.; Flores, P.F.; Silveira, L.M.. "Generating realistic stimuli for accurate power grid analysis". ACM Transactions on Design Automation of Electronic Systems 14 3 (2009): http://www.scopus.com/inward/record.url?eid=2-s2.0-67650284495&partnerID=MN8TOARS.
    10.1145/1529255.1529262
  24. Aksoy, L.; Da Costa, E.; Flores, P.; Monteiro, J.. "Exact and approximate algorithms for the optimization of area and delay in multiple constant multiplications". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27 6 (2008): 1013-1026. http://www.scopus.com/inward/record.url?eid=2-s2.0-44149085203&partnerID=MN8TOARS.
    10.1109/TCAD.2008.923242
  25. Costa, E.; Flores, P.; Monteiro, J.. "Exploiting general coefficient representation for the optimal sharing of partial products in MCMs". SBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design 2006 (2006): 161-166. http://www.scopus.com/inward/record.url?eid=2-s2.0-33750905853&partnerID=MN8TOARS.
  26. Flores, P.F.; Neto, H.C.; Marques-Silva, J.P.. "An exact solution to the minimum size test pattern problem". ACM Transactions on Design Automation of Electronic Systems 6 4 (2001): 629-644. http://www.scopus.com/inward/record.url?eid=2-s2.0-33746845358&partnerID=MN8TOARS.
    10.1145/502175.502186
  27. Flores, Paulo F.; Neto, Horacio C.; Marques-Silva, Joao P.. "On applying set covering models to test set compaction". Proceedings of the IEEE Great Lakes Symposium on VLSI (1999): 8-11. http://www.scopus.com/inward/record.url?eid=2-s2.0-0033361470&partnerID=MN8TOARS.
  28. Flores, Paulo; Costa, Jose; Neto, Horacio; Monteiro, Jose; Marques-Silva, Joao. "Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation". Proceedings of the IEEE International Conference on VLSI Design (1999): 37-41. http://www.scopus.com/inward/record.url?eid=2-s2.0-0032759312&partnerID=MN8TOARS.
  29. Flores, Paulo; Neto, Horacio; Chakrabarty, Krishnendu; Marques-Silva, Joao. "Test pattern generation for width compression in BIST". Proceedings - IEEE International Symposium on Circuits and Systems 1 (1999): http://www.scopus.com/inward/record.url?eid=2-s2.0-0032692708&partnerID=MN8TOARS.
  30. Flores, Paulo F.; Neto, Horacio C.; Marques Silva, Joao P.. "Exact solution to the minimum size test pattern problem". Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (1998): 510-515. http://www.scopus.com/inward/record.url?eid=2-s2.0-0032302181&partnerID=MN8TOARS.
  31. Manquinho, Vasco M.; Flores, Paulo F.; Silva, Joao P.Marques; Oliveira, Arlindo L.. "Prime implicant computation using satisfiability algorithms". Proceedings of the International Conference on Tools with Artificial Intelligence (1997): 232-239. http://www.scopus.com/inward/record.url?eid=2-s2.0-0031334557&partnerID=MN8TOARS.

Intellectual property

Patent
  1. Jorge R. Fernandes; Cristiano Lazzari; Flores, Paulo; José Carlos Alves Pereira Monteiro. 2013. "Tabela Multi-Valor para Dispositivos Lógicos Programáveis (Dispositivo Lógico Multi-Valor Programável)". Portugal.
    Granted/Issued
Activities

Supervision

Thesis Title
Role 		Degree Subject (Type)
Institution / Organization
2023/02 - Current Evaluation of Real Time Operating System in RISC-V
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal
2023/02 - Current Test methodology to improve verification environment for large electronic projects
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal
2023/02 - Current Sistemas tolerantes a falhas com calculos aproximados
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal
2021/03 - Current Computação aproximada para processamento de imagens de satélites em tempo-real
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2021/03 - Current On-board image processor for satellites
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2019/07 - Current A C Compiler for a RISC 16-bit Processor Supporting Embedded Applications
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2021/09 - 2022/11 Convolutional Neural Network for Hand Gesture Identification on FPGAs
Co-supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal
2019/07 - 2021/09 Develop of a C compiler and tools for educational processor
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2019 - 2021 C Compiler and Tools for P3 Educational Processor
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/09 - 2018/06 SoC Implementation of OpenMSP430 Microcontroller in UMC 130nm
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/09 - 2018/06 Extending OpenMSP430 Microcontroller for IoT Low-power Applications
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018 - 2018 SoC Implementation of OpenMSP430 Microcontroller in UMC 130nm
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 - 2017 Parallel Implementation of an Exact Filter Design Optimization Algorithm on Distributed-Memory Systems
Co-supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2014 - 2017 Optimal Implementation of LTI Systems for Embedded Real Time Applications
Co-supervisor
2015/09 - 2016/11 Systems Synthesis With Multi-Value Logic (MVL)
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/09 - 2016/11 Parallel Implementation of an Exact Filter Design Optimization Algorithm on Distributed-Memory Systems
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/09 - 2016/11 Técnicas de Computação Aproximada para Implementação de Filtros FIR
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2008/06 - 2016/06 Heterogeneous multi-core parallel structures for biological sequences alignment
Supervisor
 Engenharia Electrotécnica e de Computadores (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/09 - 2016/05 Implementation and Evaluation of a Video Decoder on the Coreworks Platform
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016 - 2016 Técnicas de Computação Aproximada para Implementação de Filtros FIR
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016 - 2016 Systems Synthesis With Multi-Value Logic (MVL)
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2014 - 2015/10 Quaternary Logic Look-up Table
Co-supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015 - 2015 Heterogeneous multi-core parallel structures for biological sequences alignment
Co-supervisor
 Engenharia Electrotécnica e de Computadores (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015 - 2015 Quaternary Logic Look-Up Table
Co-supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2013 - 2014/12 Parallel SAT Solver
Co-supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2013 - 2014/06 Parallelization of SAT Algorithms on GPU
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2012 - 2013/05 Multi-Core SIMD ASIP for DNA Sequence Alignment
Co-supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2013 - 2013 MPBO: a Distributed Pseudo-Boolean Optimization Solver
Co-supervisor
 Engenharia Informática e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2013 - 2013 Biocores - Arquitectura de um acelerador em hardware para alinhamento de sequências biológicas
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2012 - 2012 FilterAdapt - Filtros adaptativos de coeficientes variáveis
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2012 - 2012 Quaternary Logic Look-up Table
Co-supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2011 - 2011 ArqMCM - Estudo de arquitecturas para sistemas multiplicadores por múltiplas constantes
Supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal

Event organisation

Event name
Type of event (Role) 		Institution / Organization
2014/05/24 - 2015/05 IEEE International Symposium on Circuits and Systems (ISCAS), Organizador com Presidente Financeiro (Financial Chair), 2015. He was part of the organizing committee, as Financial President (Finacial Chair), of ISCAS 2015 - International Symposium on Circuits and Systems, International conference that took place in May 2015, at the Centro Cultural de Belem, which had over 1200 participants (2015/05/24 - 2015/05/27)
Conference (Member of the Organising Committee)
 IEEE Circuits and Systems Society, United States

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2008/09/10 - 2008/09/12 International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS). Local Organizer (2008/09/10 - 2008/09/12)
Conference (Member of the Organising Committee)
 Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

IEEE, United States

Jury of academic degree

Topic
Role 		Candidate name (Type of degree)
Institution / Organization
2021/03/24 Approximate and Timing-Speculative Hardware Design for High-Performance and Energy-Efficient Video Processing
(Thesis) Main arguer
 Guilherme Pereira Paim (PhD)
Universidade Federal do Rio Grande do Sul, Brazil
2021/02 Design of High-Performance Low-Noise and Low-Power Mixed-Signal CMOS Circuits Employing Self-Biasing and Low-Voltage Techniques
(Thesis) Arguer
 Somayeh Abdollahvand (PhD)
Universidade Nova de Lisboa Faculdade de Ciências e Tecnologia, Portugal
2017/05 “Implementação em FPGA de um detector de pessoas em tempo-real
(Thesis) Main arguer
 Hugo Miguel Pinheiro Torres (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016/11 Combining Support Vector Machine with Genetic Algorithms to Optimize Investments in Forex Markets With High Leverage
President of the jury
 Bernardo Martins Paiva Jubert de Almeida (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016/06 Heterogeneous multi-core parallel structures for biological sequences alignment
Supervisor
 Nuno Carlos Andre Sebastião (PhD)
Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal

Universidade de Lisboa, Portugal
2016/05 Scalable Heterogeneous Accelerating Structure for the HEVC Temporal Prediction
(Thesis) Main arguer
 Rui Manuel Alves Santiago (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016/05 Compilador para a Arquitectura Reconfigurável Versat
(Thesis) Main arguer
 Rui Manuel Alves Santiago (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/11 Offshore wind farm layout optimization regarding wake effects and electrical losses
President of the jury
 Luís Manuel Bento do Amaral (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/11 Parallel Computing applied to Analog IC Layout-Aware Sizing and Optimization
President of the jury
 David José Rodrigues Neves (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/11 Expressive Motion in Mobile Robots
President of the jury
 Maria Gard Brito de Vasconcelos Braga (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/11 Modelação da Dinâmica de um Veículo de Competição
President of the jury
 Tiago Mota Garcia de Oliveira (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/11 Efficient Implementation of Systems with Adaptive Filters
(Thesis) Main arguer
 Marta Filipa Pirão Freire (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/05 Avaliação Energética de Sistemas de Conversão Fotovoltaicos
President of the jury
 Pedro André Lourenço do Vale. (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/05 OFDM Modem Implementation Using the DSK TMS320C6416T
President of the jury
 Miguel Augusto Nogueira Mateus (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/05 Sistema de Monitorizac¸ ˜ao da Qualidade de Energia baseado em FPGA
(Thesis) Main arguer
 Jo˜ao Pedro de Matos Serra (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2014/12/29 New Eddy Current Probes and Digital Signal Processing Algorithms for Friction Stir Welding Testin
(Thesis) Main arguer
 Líis Filipe Soldado Granadeiro Rosado. (PhD)
Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal

Universidade de Lisboa, Portugal
2014/07 Secure Dynamic Reconfiguration of FPGAs
(Thesis) Main arguer
 Hirak Jyoti Kashyap (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2013/12 High-performance and Embedded Systems for Cryptography
(Thesis) Arguer
 Samuel Freitas Antão (PhD)
Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal

Universidade de Lisboa, Portugal
2010/05/28 Coverage-Directed Observability-Based Validation Method for Embedded Software
(Thesis) Main arguer
 José Carlos Campos Costa (PhD)
Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal

Universidade de Lisboa, Portugal
2010/01/28 Static and Dynamic Optimization with Insect Swarm Algorithms
(Thesis) Arguer
 Pedro Cardoso Caldas Pinto. (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2008/09/30 Efficient Simulation of Power Grids
(Thesis) Arguer
 João Manuel Santos Silva. (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal

Association member

Society Organization name Role
2013/02 - Current EEE-Institute of Electrical and Electronics Engineers IEEE Senior Member,

Committee member

Activity description
Role 		Institution / Organization
2020/10/30 - Current Coordinator of Electronics Master Programme (MEE) at Instituto Superior Técnico, Universidade de Lisboa
Coordinator
 Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/01 - 2019/12 Elected deputy coordinator of the Embedded Systems Action Line at INESC-ID, which is made up of six investigative groups, also being their representative on the Council Scientific Committee of INESC-ID Lisboa (CCIL)
Coordinator
 Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2015/01 - 2016/12 Deputy Coordinator of the Integrated Master in Electrotechnical Engineering and IST Computers (MEEC)
Coordinator
 Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal

Consulting

Activity description Institution / Organization
2014 - 2017/03 Due to their personal characteristics and technical knowledge in reconfigurable systems, was chosen by the partner for non-executive administrator at Coreworks, position assumed since January 2014. Coreworks was founded in 2001, assuming itself as leading company in providing SIP (Semiconductor Intellectual Property) solutions for multiple standards and multimedia platforms. Its products are based on technology proprietary SideWorks that allows you to develop reconfigurable hardware accelerators, these being prototype in FPGAs and VLSI
2001 - 2004 Founding partner of start-up Iknow. Taking advantage of the expansion of the Internet at the beginning of the century, Iknow came up with the offer of configurable simulators integrated in an accessible platform over the network. He then specialized in the banking market providing workflow solutions configurations supported by the Web. This characteristic, innovative at the time, allowed the creation and use of several centrally defined workflows, but used in all branches at the level national bank tp carry out the credit simulation.

Evaluation committee

Activity description
Role 		Institution / Organization Funding entity
2018/12 - 2018/12 Exploração de Computação Aproximada no Projeto de Hardware Dedicado de Baixo Consumo para a Codificação de Vídeo em Dispositivos Móveis.
Evaluator
 Universidade Federal de Pelotas, Brazil

Journal scientific committee

Journal title (ISSN) Publisher
2021 - 2022 Algorithms (ISSN 1999-4893) (1999-4893) Academic Open Access Publishing
2020 - 2021 Electronics (ISSN 2079-9292) (2079-9292) Academic Open Access Publishing.
Distinctions

Award

2015 Best Paper Award
13th13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC), Portugal
2013 Prémio Prof. Luís Vidigal
Instituto Superior Técnico Departemento de Engenharia Electrotécnica e de Computadores, Portugal
2010 Best Paper Award
VI Jornadas sobre Sistemas Reconfiguráveis (REC), Portugal

Title

2013 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC
IEEE, United States

Other distinction

2014 3rd place on SAT Competition 2014 (Parallel, Hard-combinatorial SAT+UNSAT track)
2013 IEEE Senior Member
2013 3rd place on SAT Competition 2013 (Core Solvers, Parallel, Hard-combinatorial SAT+UNSAT)
2013 Jorge Fernandes, Cristiano Lazzari, Paulo Flores, Jose Monteiro ´ . Tabela Multi-Valor para Dispositivos Logicos Program ´ aveis ´ (Dispositivo Logico Multi-Valor Program ´ avel) ´ Patente de Invenc¸ao Nacional nº 105282 ˜ ,
2011 Winner - Programming Challenge Workshop on GPU Programming
2011 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC
Instituto Nacional da Propriedade Industrial IP, Portugal