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Identification

Personal identification

Full name
Jorge Filipe Leal Costa Semião

Citation names

  • Semião, Jorge
  • J. Semião

Author identifiers

Ciência ID
B616-9C41-C169
ORCID iD
0000-0002-7667-7910

Websites

Knowledge fields

  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Electrical and Electronic Engineering
Education
Degree Classification
2010/07/13
Concluded
 Engenharia Electrotécnica e de Computadores (Doutoramento)
Major in Microelectrónica
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Metodologias Baseadas na Tensão de Alimentação e Temperatura para Melhorar a Tolerância e a Detecção de Faltas Dinâmicas em Sistemas Integrados Digitais" (THESIS/DISSERTATION)
2001/05/15
Concluded
 Engenharia Electrotécnica e de Computadores (Mestrado)
Major in Sistemas Electrónicos e Computadores
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Técnicas de Introdução de DFT a Nível de Sistema em Sistemas Físicos e Lógicos (Hw/Sw)" (THESIS/DISSERTATION)
 5/5
1996/10/03
Concluded
 Engenharia Electrotécnica e de Computadores (Licenciatura)
Major in Sistemas Electrónicos e Computadores
Universidade de Lisboa Instituto Superior Técnico, Portugal
 14
Affiliation

Teaching in Higher Education

Category
Host institution 		Employer
2001/05/15 - Current Adjunct Teacher (Polytechnic Teacher) Universidade do Algarve Instituto Superior de Engenharia, Portugal
2016 - 2019 Adjunct Teacher (Polytechnic Teacher) Universidade do Algarve, Portugal
2013 - 2016 Adjunct Teacher (Polytechnic Teacher) Universidade do Algarve Instituto Superior de Engenharia, Portugal
1997/09/22 - 2001/05/14 Assistant (Polytechnic Teacher) Universidade do Algarve Instituto Superior de Engenharia, Portugal

Positions / Appointments

Category
Host institution 		Employer
2016 - 2019 Conselho científico/técnico-científico ou orgão correspondente Universidade do Algarve, Portugal
2016 - 2019 Coordenação ou direção de centro de investigação, departamento ou equivalente Universidade do Algarve, Portugal
2015 - 2016 Conselho científico/técnico-científico ou orgão correspondente Universidade do Algarve Instituto Superior de Engenharia, Portugal
2015 - 2016 Coordenação ou direção de centro de investigação, departamento ou equivalente Universidade do Algarve Instituto Superior de Engenharia, Portugal
2013 - 2014 Coordenação ou direção de centro de investigação, departamento ou equivalente Universidade do Algarve Instituto Superior de Engenharia, Portugal
Projects

Contract

Designation Funders
2009/01/01 - 2012/03/31 Nanoelectrónica para aplicações na indústria automovel SE2A
ENIAC/NTec/0002/2008
INESC Microsistemas e Nanotecnologias, Portugal

INOV INESC INOVAÇÃO - Instituto de Novas Tecnologias, Portugal

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Fundação para a Ciência e a Tecnologia
Concluded
2006/01/01 - 2009/12/31 METODOLOGIAS BASEADAS NA TENSÃO DE ALIMENTAÇÃO E TEMPERATURA PARA MELHORAR A TOLERÂNCIA E A DETECÇÃO DE FALTAS DINÂMICAS EM SISTEMAS INTEGRADOS DIGITAIS
SFRH/BD/24609/2005
 Fundação para a Ciência e a Tecnologia
Concluded
2005/01/01 - 2008/03/31 Teste Dinâmico de Sistemas Integrados em Nanotecnologias
POSC/EEA-ESE/57405/2004
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Universidade do Algarve, Portugal
Fundação para a Ciência e a Tecnologia
Concluded
2006/09/01 - 2007/10/31 Colaboração na Experiência CMS no CERN
POCI/FP/63922/2005
Laboratório de Instrumentação e Física Experimental de Partículas Coimbra, Portugal

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Fundação para a Ciência e a Tecnologia
Concluded
2005/08/01 - 2006/09/30 Colaboração na Experiência CMS no CERN
POCI/FP/63434/2005
Laboratório de Instrumentação e Física Experimental de Partículas Coimbra, Portugal

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Fundação para a Ciência e a Tecnologia
Concluded
Outputs

Publications

Book chapter
  1. Pedro J. S. Cardoso; Jânio Monteiro; Cristiano Cabrita; Jorge Semião; Dario Medina Cruz; Nelson Pinto; Célia M.Q. Ramos; Luís M. R. Oliveira; João M. F. Rodrigues. "Monitoring, Predicting, and Optimizing Energy Consumptions". In A Goal Toward Global Sustainability, 20-47. {IGI, 2021.
    10.4018/978-1-7998-9152-9.ch002
  2. J. Semião; H. Santos; R. Cabral; M. B. Santos; P. Teixeira. "PVTA-Aware Performance SRAM Sensor for IoT Applications". 2020.
    10.1007/978-3-030-30938-1_27
  3. J. D. Mozo; J. I. Otero; E. Durán; Jorge Semião. "An Open Hardware Electronic Controller for Motorized Rotary Injection Valves Used in Flow Injection Analysis". 259-267. Springer International Publishing, 2018.
    10.1007/978-3-319-70272-8_22
Conference paper
  1. Mozo, J. D.; Otero, J. I.; Durán, E.; Semião, Jorge. "An open hardware electronic controller for motorized rotary injection valves used in Flow Injection Analysis". 2018.
    10.1007/978-3-319-70272-8_22
  2. Cardoso, PJS; Schuetz, G; Semiao, J; Monteiro, J; Rodrigues, J; Mazayev, A; Ey, E; Viegas, M. "Integration of a Real-Time Stochastic Routing Optimization Software with an Enterprise Resource Planner". 2016.
    10.1007/978-3-319-29589-3_8
  3. Santos, H; Semiao, J; Cabral, R; Romao, A; Santos, MB; Teixeira, IC; Teixeira, JP. "Aging and Performance Sensor for SRAM". 2016.
    10.1109/dcis.2016.7845354
  4. Leong, C; Semiao, J; Santos, MB; Teixeira, IC; Teixeira, JP. "Fault-Tolerance in FPGA Focusing Power Reduction or Performance Enhancement". 2015.
    10.1109/latw.2015.7102523
  5. Leong, C; Semiao, J; Santos, MB; Teixeira, IC; Teixeira, JP; Batista, AJN; Goncalves, B; Marques, JG. "Fast Radiation Monitoring in FPGA-based Designs". 2015.
    10.1109/dcis.2015.7388590
  6. Semiao, J; Leong, C; Romao, A; Santos, MB; Teixeira, IC; Teixeira, JP. "Aging-aware dynamic voltage or frequency scaling". 2014.
    10.1109/dcis.2014.7035599
  7. Semião, Jorge. "Aging Monitoring with Local Sensors in FPGA-based Designs". 2013.
    http://dx.doi.org/10.1109/FPL.2013.6645596
  8. Leong, C; Semiao, J; Teixeira, IC; Santos, MB; Teixeira, JP; Valdes, M; Freijedo, J; Rodriguez Andina, JJ; Vargas, F. "AGING MONITORING WITH LOCAL SENSORS IN FPGA-BASED DESIGNS". 2013.
    10.1109/fpl.2013.6645596
  9. Pachito, J; Martins, CV; Semiao, J; Santos, M; Teixeira, IC; Teixeira, JP. "The Influence of Clock-Gating On NBTI-Induced Delay Degradation". 2012.
    10.1109/iolts.2012.6313842
  10. Valdes, M; Freijedo, J; Moure, MJ; Rodriguez Andina, JJ; Semiao, J; Vargas, F; Teixeira, IC; Teixeira, JP. "Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects". 2011.
    10.1109/latw.2011.5985926
  11. Oliveira, RS; Semiao, J; Teixeira, IC; Santos, MB; Teixeira, JP. "On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications". 2011.
    10.1109/latw.2011.5985919
  12. Freijedo, J; Semiao, J; Rodriguez Andina, JJ; Vargas, F; Teixeira, IC; Teixeira, JP. "Modeling the effect of process variations on the timing response of nanometer digital circuits". 2011.
    10.1109/latw.2011.5985927
  13. Bexiga, V; Leong, C; Semiao, J; Teixeira, I; Teixeira, JP; Valdes, M; Freijedo, J; Rodriguez Andina, JJ; Vargas, F. "Performance failure prediction using built-in delay sensors in FPGAs". 2011.
    10.1109/fpl.2011.61
  14. Martins, CV; Semiao, J; Vazquez, JC; Champac, V; Santos, M; Teixeira, IC; Teixeira, JP. "Adaptive Error-Prediction Flip-flop for Performance Failure Prediction with Aging Sensors". 2011.
    10.1109/vts.2011.5783784
  15. Vazquez, JC; Champac, V; Ziesemer, AM; Reis, R; Semiao, J; Teixeira, IC; Santos, MB; Teixeira, JP. "Predictive error detection by on-line aging monitoring". 2010.
    10.1109/iolts.2010.5560241
  16. Chipana, R; Bolzani, L; Vargas, F; Semiao, J; Rodriguez Andina, J; Teixeira, I; Teixeira, P. "Investigating the use of BICS to detect resistive- open defects in SRAMs". 2010.
    10.1109/iolts.2010.5560207
  17. Freijedo, JF; Valdes, MD; Moure, MJ; Costas, L; Rodriguez Andina, JJ; Semiao, J; Vargas, F; Teixeira, IC; Teixeira, JP. "Delay modeling for power noise-aware design in Spartan-3A FPGAS". 2010.
    10.1109/spl.2010.5483026
  18. Semiao, J; Freijedo, J; Moraes, M; Mallmann, M; Antunes, C; Benfica, J; Vargas, F; et al. "Measuring Clock-Signal Modulation Efficiency for Systems-on-Chip in Electromagnetic Interference Environment". 2009.
    10.1109/latw.2009.4813817
  19. Semiao, J; Freijedo, J; Rodriguez Andina, J; Vargas, F; Santos, M; Teixeira, I; Teixeira, P. "Delay-Fault Tolerance to Power Supply Voltage Disturbances Analysis in Nanometer Technologies". 2009.
    10.1109/iolts.2009.5196020
  20. Semiao, J; Varela, J; Freijedo, J; Andina, J; Leong, C; Teixeira, JP; Teixeira, I. "Robust Solution for Synchronous Communication among Multi Clock Domains". 2008.
    10.1109/apccas.2008.4746218
  21. Semiao, J; Freijedo, J; Moraes, M; Mallmann, M; Antunes, C; Rocha, L; Benfica, J; et al. "Power-Supply Instability Aware Clock Signal Modulation for Digital Integrated Circuits". 2008.
    10.1109/emceurope.2008.4786876
  22. Semiao, J; Rodriguez Andina, JJ; Vargas, F; Santos, M; Teixeira, I; Teixeira, P. "Process tolerant design using thermal and power-supply tolerance in pipeline based circuits". 2008.
    10.1109/ddecs.2008.4538752
  23. Semiao, J; Freijedo, J; Andina, J; Vargas, F; Santos, M; Teixeira, I; Teixeira, P. "Exploiting parametric power supply and/or temperature variations to improve fault tolerance in digital circuits". 2008.
    10.1109/iolts.2008.51
  24. Semiao, J; Freijedo, J; Andina, JJR; Vargas, F; Santos, MB; Teixeira, IC; Teixeira, JP. "Enhancing the tolerance to power-supply instability in digital circuits". 2007.
    10.1109/isvlsi.2007.44
  25. Semiao, J; Freijedo, J; Rodiriguez Andina, JJ; Vargas, F; Santos, MB; Teixeira, IC; Teixeira, JP. "Improving tolerance to power-supply and temperature variations in synchronous circuits". 2007.
    10.1109/ddecs.2007.4295299
  26. Semiao, J; Freijedo, J; Rodriguez Andina, JJ; Vargas, F; Santos, MB; Teixeira, IC; Teixeira, JP. "On-line dynamic delay insertion to improve signal integrity in synchronous circuits". 2007.
    10.1109/iolts.2007.49
  27. Semiao, J; Rodriguez Andina, JJ; Vargas, F; Santos, MB; Teixeira, IC; Teixeira, JP. "Improving the tolerance of pipeline based circuits to power supply or temperature variations". 2007.
    10.1109/dft.2007.60
  28. Guerreiro, F; Semiao, J; Pierce, A; Santos, M; Teixeira, I. "Functional-oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage". 2006.
    10.1109/ddecs.2006.1649635
  29. Rodriguez Irago, M; Andina, JJR; Vargas, F; Semiao, J; Teixeira, IC; Teixeira, JP. "Dynamic fault detection in digital systems using dynamic voltage scaling and multi-temperature schemes". 2006.
    10.1109/iolts.2006.25
  30. Semiao, J; Rodriguez Andina, JJ; Vargas, F; Santos, MB; Teixeira, IC; Teixeira, JP. "Improving the tolerance of pipeline based circuits to power supply or temperature variations". 2005.
  31. Teixeira, JP; Teixeira, IM; Pereira, CE; Dias, OP; Semiao, J. "Test resource partitioning: a design & test issue". 2001.
    10.1109/date.2001.914997
Journal article
  1. Litrán, Salvador P.; Durán, Eladio; Semião, Jorge; Barroso, Rafael S.. "Single-switch bipolar output DC-DC converter for photovoltaic application". (2020): http://hdl.handle.net/10400.1/14669.
    10.3390/electronics9071171
  2. Sartelli, Massimo; Abu-Zidan, Fikri M.; Labricciosa, Francesco M.; Kluger, Yoram; Coccolini, Federico; Ansaloni, Luca; Leppäniemi, Ari; et al. "Physiological parameters for Prognosis in Abdominal Sepsis (PIPAS) Study: a WSES observational study". (2019): http://hdl.handle.net/1822/67380.
    10.1186/s13017-019-0253-2
  3. Cardoso, Pedro J. S.; Schuetz, Gabriela; Semiao, Jorge; Monteiro, Janio; Rodrigues, Joao; Mazayev, Andriy; Ey, Emanuel; Viegas, Micael. "Integration of a real-time stochastic routing optimization software with an enterprise resource planner". (2016): http://hdl.handle.net/10400.1/9764.
    10.1007/978-3-319-29589-3_8
  4. Leong, C; Semiao, J; Santos, MB; Teixeira, IC; Teixeira, JP. "Fault-Tolerance in Field Programmable Gate Array with Dynamic Voltage and Frequency Scaling". JOURNAL OF LOW POWER ELECTRONICS (2015):
    10.1166/jolpe.2015.1406
  5. Valdes-Pena, M.D.; Fernandez Freijedo, J.; Moure Rodriguez, M.J.; Rodriguez-Andina, J.J.; Semiao, J.; Teixeira, I.M.C.; Teixeira, J.P.C.; Vargas, F.. "Design and validation of configurable online aging sensors in nanometer-scale FPGAs". IEEE Transactions on Nanotechnology 12 4 (2013): 508-517. http://www.scopus.com/inward/record.url?eid=2-s2.0-84880423896&partnerID=MN8TOARS.
    10.1109/TNANO.2013.2253795
  6. Vazquez, J.C.; Champac, V.; Semião, J.; Teixeira, I.C.; Santos, M.B.; Teixeira, J.P.. "Process variations-aware statistical analysis framework for aging sensors insertion". Journal of Electronic Testing: Theory and Applications (JETTA) 29 3 (2013): 289-299. http://www.scopus.com/inward/record.url?eid=2-s2.0-84880076511&partnerID=MN8TOARS.
    10.1007/s10836-013-5358-z
  7. Valdes Pena, MD; Fernandez Freijedo, JF; Moure Rodriguez, MJM; Rodriguez Andina, JJ; Semiao, J; Cacho Teixeira, IMC; Cacho Teixeira, JPC; Vargas, F. "Design and Validation of Configurable Online Aging Sensors in Nanometer-Scale FPGAs". IEEE TRANSACTIONS ON NANOTECHNOLOGY (2013):
    10.1109/tnano.2013.2253795
  8. Freijedo, J.F.; Semiäo, J.; Rodriguez-Andina, J.J.; Vargas, F.; Teixeira, I.C.; Teixeira, J.P.. "Modeling the effect of process, power-supply voltage and temperature variations on the timing response of nanometer digital circuits". Journal of Electronic Testing: Theory and Applications (JETTA) 28 4 (2012): 421-434. http://www.scopus.com/inward/record.url?eid=2-s2.0-84867231291&partnerID=MN8TOARS.
    10.1007/s10836-012-5297-0
  9. Pachito, J.; Martins, C.V.; Jacinto, B.; Semião, J.; Vazquez, J.C.; Champac, V.; Santos, M.B.; Teixeira, I.C.; Teixeira, J.P.. "Aging-aware power or frequency tuning with predictive fault detection". IEEE Design and Test of Computers 29 5 (2012): 27-36. http://www.scopus.com/inward/record.url?eid=2-s2.0-84873052843&partnerID=MN8TOARS.
    10.1109/MDT.2012.2206009
  10. Pachito, J.; Martins, C.V.; Semiao, J.; Santos, M.; Teixeira, I.C.; Teixeira, J.P.. "The influence of clock-gating on NBTI-induced delay degradation". Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012 (2012): 61-66. http://www.scopus.com/inward/record.url?eid=2-s2.0-84869201850&partnerID=MN8TOARS.
    10.1109/IOLTS.2012.6313842
  11. Pachito, J; Martins, CV; Jacinto, B; Teixeira, IC; Teixeira, JP; Semiao, J; Vazquez, JC; Champac, V; Santos, MB. "Aging-Aware Power or Frequency Tuning With Predictive Fault Detection". IEEE DESIGN & TEST OF COMPUTERS (2012):
    10.1109/mdt.2012.2206009
  12. Silva, D.; Poehls, L.B.; Semião, J.; Teixeira, I.C.; Teixeira, J.P.; Valdés, M.; Freijedo, J.; Rodríguez-Andina, J.J.; Vargas, F.. "IP core to leverage RTOS-based embedded systems reliability to electromagnetic interference". Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011 (2011): 119-124. http://www.scopus.com/inward/record.url?eid=2-s2.0-84856994091&partnerID=MN8TOARS.
  13. Oliveira, R.S.; Semião, J.; Teixeira, I.C.; Santos, M.B.; Teixeira, J.P.. "On-line BIST for performance failure prediction under NBTI-induced aging in safety-critical applications". Journal of Low Power Electronics 7 4 (2011): 562-572. http://www.scopus.com/inward/record.url?eid=2-s2.0-84857267074&partnerID=MN8TOARS.
    10.1166/jolpe.2011.1155
  14. Bexiga, V.; Leong, C.; Semião, J.; Teixeira, Ic.; Teixeira, J.P.; Valdés, M.; Freijedo, J.; Rodríguez-Andina, J.J.; Vargas, F.. "Performance failure prediction using built-in delay sensors in FPGAs". Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011 (2011): 301-304. http://www.scopus.com/inward/record.url?eid=2-s2.0-80455127093&partnerID=MN8TOARS.
    10.1109/FPL.2011.61
  15. Freijedo, J.; Semião, J.; Rodríguez-Andina, J.J.; Vargas, F.; Teixeira, I.C.; Teixeira, J.P.. "Modeling the effect of process variations on the timing response of nanometer digital circuits". LATW 2011 - 12th IEEE Latin-American Test Workshop (2011): http://www.scopus.com/inward/record.url?eid=2-s2.0-80052617161&partnerID=MN8TOARS.
    10.1109/LATW.2011.5985927
  16. Valdés, M.; Freijedo, J.; Moure, M.J.; Rodríguez-Andina, J.J.; Semião, J.; Vargas, F.; Teixeira, I.C.; Teixeira, J.P.. "Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects". LATW 2011 - 12th IEEE Latin-American Test Workshop (2011): http://www.scopus.com/inward/record.url?eid=2-s2.0-80052620010&partnerID=MN8TOARS.
    10.1109/LATW.2011.5985926
  17. Oliveira, R.S.; Semião, J.; Teixeira, I.C.; Santos, M.B.; Teixeira, J.P.. "On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications". LATW 2011 - 12th IEEE Latin-American Test Workshop (2011): http://www.scopus.com/inward/record.url?eid=2-s2.0-80052615301&partnerID=MN8TOARS.
    10.1109/LATW.2011.5985919
  18. Martins, C.V.; Semião, J.; Vazquez, J.C.; Champac, V.; Santos, M.; Teixeira, I.C.; Teixeira, J.P.. "Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors". Proceedings of the IEEE VLSI Test Symposium (2011): 203-208. http://www.scopus.com/inward/record.url?eid=2-s2.0-79959649877&partnerID=MN8TOARS.
    10.1109/VTS.2011.5783784
  19. Freijedo, J.; Valdés, M.D.; Costas, L.; Moure, M.J.; Rodríguez-Andina, J.J.; Semião, J.; Vargas, F.; Teixeira, I.C.; Teixeira, J.P.. "Lower V DD operation of FPGA-based digital circuits through delay modeling and time borrowing". Journal of Low Power Electronics 7 2 (2011): 185-198. http://www.scopus.com/inward/record.url?eid=2-s2.0-84856972351&partnerID=MN8TOARS.
    10.1166/jolpe.2011.1127
  20. Chipana, R.; Bolzani, L.; Vargas, F.; Semião, J.; Rodríguez-Andina, J.; Teixeira, I.; Teixeira, P.. "Investigating the use of BICS to detect resistive- open defects in SRAMs". Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010 (2010): 200-201. http://www.scopus.com/inward/record.url?eid=2-s2.0-77957992089&partnerID=MN8TOARS.
    10.1109/IOLTS.2010.5560207
  21. Vazquez, J.C.; Champac, V.; Ziesemer Jr., A.M.; Reis, R.; Semião, J.; Teixeira, I.C.; Santos, M.B.; Teixeira, J.P.. "Predictive error detection by on-line aging monitoring". Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010 (2010): 9-14. http://www.scopus.com/inward/record.url?eid=2-s2.0-77957996888&partnerID=MN8TOARS.
    10.1109/IOLTS.2010.5560241
  22. Freijedo, J.; Costas, L.; Semião, J.; Rodríguez-Andina, J.J.; Moure, M.J.; Vargas, F.; Teixeira, I.C.; Teixeira, J.P.. "Impact of power supply voltage variations on FPGA-based digital systems performance". Journal of Low Power Electronics 6 2 (2010): 339-349. http://www.scopus.com/inward/record.url?eid=2-s2.0-77955690901&partnerID=MN8TOARS.
    10.1166/jolpe.2010.1076
  23. Freijedo, J.F.; Valdés, M.D.; Moure, M.J.; Costas, L.; Rodríguez-Andina, J.J.; Semião, J.; Vargas, F.; Teixeira, I.C.; Teixeira, J.P.. "Delay modeling for power noise-aware design in Spartan-3A FPGAS". 6th Southern Programmable Logic Conference, SPL 2010 - Proceedings (2010): 127-132. http://www.scopus.com/inward/record.url?eid=2-s2.0-77954443764&partnerID=MN8TOARS.
    10.1109/SPL.2010.5483026
  24. Semião, J.; Freijedo, J.; Rodriguez-Andina, J.; Vargas, F.; Santos, M.; Teixeira, I.; Teixeira, P.. "Delay-fault tolerance to power supply voltage disturbances analysis in nanometer technologies". 2009 15th IEEE International On-Line Testing Symposium, IOLTS 2009 (2009): 223-228. http://www.scopus.com/inward/record.url?eid=2-s2.0-70449416225&partnerID=MN8TOARS.
    10.1109/IOLTS.2009.5196020
  25. Semiao, J.; Freijedo, J.; Moraes, M.; Mallmann, M.; Antunes, C.; Benfica, J.; Vargas, F.; et al. "Measuring clock-signal modulation efficiency for systems-on-chip in electromagnetic interference environment". 2009 10th Latin American Test Workshop, LATW 2009 (2009): http://www.scopus.com/inward/record.url?eid=2-s2.0-67649833995&partnerID=MN8TOARS.
    10.1109/LATW.2009.4813817
  26. Freijedo, J.F.; Semião, J.; Rodríguez-Andina, J.J.; Vargas, F.; Teixeira, I.C.; Teixeira, J.P.. "Delay modeling for power noise and temperature-aware design and test of digital systems". Journal of Low Power Electronics 4 3 (2008): 385-391. http://www.scopus.com/inward/record.url?eid=2-s2.0-67649512879&partnerID=MN8TOARS.
    10.1166/jolpe.2008.191
  27. Semião, J.; Freijedo, J.; Moraes, M.; Mallmann, M.; Antunes, C.; Rocha, L.; Benfica, J.; et al. "Power-supply instability aware clock signal modulation for digital integrated circuits". IEEE International Symposium on Electromagnetic Compatibility (2008): http://www.scopus.com/inward/record.url?eid=2-s2.0-63549141280&partnerID=MN8TOARS.
    10.1109/EMCEUROPE.2008.4786876
  28. Semião, J.; Freijedo, J.F.; Rodriguez-Andina, J.J.; Vargas, F.; Santos, M.B.; Teixeira, I.C.; Teixeira, J.P.. "Time Management for Low-Power Design of Digital Systems". Journal of Low Power Electronics 4 3 (2008): 410-419. http://www.scopus.com/inward/record.url?eid=2-s2.0-67649562607&partnerID=MN8TOARS.
    10.1166/jolpe.2008.194
  29. Semião, J.F.L.C.; Irago, M.J.R.; Rodrïuez-Andina, J.J.; Piccoli, L.B.; Vargas, F.L.; dos Santos, M.B.; Teixeira, I.M.C.; Teixeira, J.P.. "Signal integrity enhancement in digital circuits". IEEE Design and Test of Computers 25 5 (2008): 452-461. http://www.scopus.com/inward/record.url?eid=2-s2.0-55349113251&partnerID=MN8TOARS.
    10.1109/MDT.2008.146
  30. Semião, J.; Freijedo, J.; Andina, J.; Vargas, F.; Santos, M.; Teixeira, I.; Teixeira, P.. "Exploiting parametric power supply and/or temperature variations to improve fault tolerance in digital circuits". Proceedings - 14th IEEE International On-Line Testing Symposium, IOLTS 2008 (2008): 227-232. http://www.scopus.com/inward/record.url?eid=2-s2.0-52049084093&partnerID=MN8TOARS.
    10.1109/IOLTS.2008.51
  31. Semião, J.; Rodriguez-Andina, J.J.; Vargas, F.; Santos, M.; Teixeira, I.; Teixeira, P.. "Process tolerant design using thernal and power-supply tolerance in pipeline based circuits". Proceedings - 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS (2008): 34-37. http://www.scopus.com/inward/record.url?eid=2-s2.0-50649098809&partnerID=MN8TOARS.
    10.1109/DDECS.2008.4538752
  32. Semiao, JFLC; Rodriguez Irago, MJR; Rodriguez Andina, JJ; Piccoli, LB; Vargas, FL; dos Santos, MB; Cacho Teixeira, IMC; Teixeira, JP. "Signal integrity enhancement in digital circuits". IEEE DESIGN & TEST OF COMPUTERS (2008):
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    10.1109/APCCAS.2008.4746218
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    10.1109/IOLTS.2007.49
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    10.1109/DFT.2007.60
  37. Semião, J.; Freijedo, J.; Rodríguez Andina, J.J.; Vargas, F.; Santos, M.B.; Teixeira, I.C.; Teixeira, J.P.. "Enhancing the tolerance to power-supply instability in digital circuits". Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (2007): 207-212. http://www.scopus.com/inward/record.url?eid=2-s2.0-36349032171&partnerID=MN8TOARS.
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  38. Guerreiro, F.; Semião, J.; Pierce, A.; Santos, M.B.; Teixeira, I.M.; Teixeira, J.P.. "Functional-oriented BIST of sequential circuits aiming at dynamic faults coverage". 2006 IEEE Design and Diagnostics of Electronic Circuits and systems 2006 (2006): 277-282. http://www.scopus.com/inward/record.url?eid=2-s2.0-33847120256&partnerID=MN8TOARS.
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  39. Rodríguez-Irago, M.; Andina, J.J.R.; Vargas, F.; Semião, J.; Teixeira, I.C.; Teixeira, J.P.. "Dynamic fault detection in digital systems using dynamic voltage scaling and multi-temperature schemes". Proceedings - IOLTS 2006: 12th IEEE International On-Line Testing Symposium 2006 (2006): 257-262. http://www.scopus.com/inward/record.url?eid=2-s2.0-34247221599&partnerID=MN8TOARS.
    10.1109/IOLTS.2006.25
Thesis / Dissertation
  1. Santos, Luís Mário Braz dos. "Performance sensor for CMOS memory cells". Master, 2020. http://hdl.handle.net/10400.1/15380.
  2. Cavalaria, Hugo Alexandre Nunes. "Automatic analysis of subthreshold operation in CMOS digital circuits". Master, 2018. http://hdl.handle.net/10400.1/10972.
  3. Sardo, João Duarte Pereira. "Portable device for augmented reality: five-sense experiences". Master, 2017. http://hdl.handle.net/10400.1/10402.
  4. Costa, Hugo Miguel Conceição. "Sistema de monitorização e previsão inteligente de consumos elétricos". Master, 2016. http://hdl.handle.net/10400.1/8306.
  5. Conceição, Abel Jorge Gonçalves da. "Projeto de soluções confiáveis de automação em ambiente industrial". Master, 2016. http://hdl.handle.net/10400.1/9851.
  6. Santos, Hugo Fernandes da Silva. "Aging sensor for CMOS memory cells". Master, 2016. http://hdl.handle.net/10400.1/8028.
  7. Vasconcelos, Sérgio Ricardo Martins. "Sistema remoto para monitorização de ambientes refrigerados em viaturas automóveis". Master, 2015. http://hdl.handle.net/10400.1/7916.
  8. Tinoco, Mário Jorge de Aguiar Laranjo. "Sistema de aquisição para monitorização da produção de energia em sistemas de energia renovável". Master, 2014. http://hdl.handle.net/10400.1/8372.
  9. Romão, André Azevedo de Sousa. "Dynamic power and frequency optimization in digital electronic systems". Master, 2013. http://hdl.handle.net/10400.1/5990.
  10. Coelho, João Ricardo dos Santos. "Aging monitoring methodology for built-In self-test applications". Master, 2013. http://hdl.handle.net/10400.1/6899.
  11. Pachito, Jakson dos Santos. "Metodologia para prever o envelhecimento de circuitos digitais". Master, 2012. http://hdl.handle.net/10400.1/3250.
  12. Martins, Celestino Virtudes Dias. "Adaptive error-prediction aging sensor for synchronous digital circuits". Master, 2012. http://hdl.handle.net/10400.1/3280.
Activities

Supervision

Thesis Title
Role 		Degree Subject (Type)
Institution / Organization
2020 - 2020 PERFORMANCE SENSOR FOR CMOS MEMORY CELLS - SENSOR DE PERFORMANCE PARA CÉLULAS DE MEMÓRIA CMOS
Supervisor
 Engenharia Eletrotécnica e de Computadores (Master)
Universidade do Algarve Instituto Superior de Engenharia, Portugal
2018 - 2018 Automatic Analysis of Subthreshold Operation in CMOS Digital Circuits
Supervisor
 Engenharia Eléctrica e Electrónica (Master)
Universidade do Algarve Instituto Superior de Engenharia, Portugal
2016 - 2016 Projeto de soluções confiáveis de automação em ambiente industrial
Supervisor
 Engenharia Eléctrica e Electrónica (Master)
Universidade do Algarve Instituto Superior de Engenharia, Portugal
2016 - 2016 AGING SENSOR FOR CMOS MEMORY CELLS
Supervisor
 Engenharia Eléctrica e Electrónica (Master)
Universidade do Algarve Instituto Superior de Engenharia, Portugal
2015 - 2015 SISTEMA REMOTO PARA MONITORIZAÇÃO DE AMBIENTES REFRIGERADOS EM VIATURAS AUTOMÓVEIS
Supervisor
 Engenharia Eléctrica e Electrónica (Master)
Universidade do Algarve Instituto Superior de Engenharia, Portugal
2015 - 2015 SISTEMA DE AQUISIÇÃO PARA MONITORIZAÇÃO DA PRODUÇÃO DE ENERGIA EM SISTEMAS DE ENERGIA RENOVÁVEL
Supervisor
 Engenharia Eléctrica e Electrónica (Master)
Universidade do Algarve Instituto Superior de Engenharia, Portugal
2014 - 2014 Aging monitoring methodology for built-In self-test applications Metodologia de monitorização do envelhecimento para aplicações de auto-teste embutido
Supervisor
 Engenharia Eléctrica e Electrónica (Master)
Universidade do Algarve Instituto Superior de Engenharia, Portugal
2013 - 2013 Dynamic power and frequency optimization in digital electronic systems
Supervisor
 Engenharia Eléctrica e Electrónica (Master)
Universidade do Algarve Instituto Superior de Engenharia, Portugal
2012 - 2012 METODOLOGIA PARA PREVER O ENVELHECIMENTO DE CIRCUITOS DIGITAIS
Supervisor
 Engenharia Eléctrica e Electrónica (Master)
Universidade do Algarve Instituto Superior de Engenharia, Portugal
Distinctions

Other distinction

2010 Best INESC-ID Ph.D Student 2010 Award
2001 Melhor Estágio - Engenharia Electrotécnica
Ordem dos Engenheiros, Portugal
1999 Melhor Professor do Curso de Engª Eléctrica e Electrónica da EST - UAlg.