Personal identification

Full name

Luís Jorge Brás Monteiro Guerra e Silva

Author identifiers

Ciência ID

A814-B971-59F6

Knowledge fields

• Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Electrical and Electronic Engineering

Languages

Language	Speaking	Reading	Writing	Listening	Peer-review
English	Proficiency (C2)	Proficiency (C2)	Proficiency (C2)	Proficiency (C2)

Science

	Category Host institution	Employer
2000/04 - Current	Researcher (Research)	Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
	Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2005/07 - 2006/08	Research Trainee (Research)	Cadence Design Systems Inc, United States
	Cadence Design Systems Inc, United States
1996/12 - 2000/03	Research Assistant (Research)	Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
	Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
1999/07 - 1999/09	Research Trainee (Research)	IBM Thomas J Watson Research Center, United States
	IBM Thomas J Watson Research Center, United States
1995/10 - 1996/11	Research Trainee (Research)	Instituto de Engenharia de Sistemas e Computadores, Portugal
	Instituto de Engenharia de Sistemas e Computadores, Portugal

Teaching in Higher Education

	Category Host institution	Employer
2009/05 - Current	Assistant Professor (University Teacher)	Universidade de Lisboa Instituto Superior Técnico, Portugal
	Universidade de Lisboa Instituto Superior Técnico, Portugal
2000/04 - 2009/04	Assistant (University Teacher)	Universidade de Lisboa Instituto Superior Técnico, Portugal
	Universidade de Lisboa Instituto Superior Técnico, Portugal
1999/04 - 1999/09	Trainee Assistant (University Teacher)	Universidade de Lisboa Instituto Superior Técnico, Portugal
	Universidade de Lisboa Instituto Superior Técnico, Portugal

Positions / Appointments

	Category Host institution	Employer
2014/10 - 2020/01/02	Vice-President of the Board for Information & Communication Technologies	Universidade de Lisboa Instituto Superior Técnico, Portugal
	Universidade de Lisboa Instituto Superior Técnico, Portugal
2013/01 - 2014/09	Vice-President of the Computer and Network Services Division (DSI)	Universidade de Lisboa Instituto Superior Técnico, Portugal
	Universidade de Lisboa Instituto Superior Técnico, Portugal

Grant

	Designation	Funders
2018/10/01 - Current	DOME: Discrete Optimization Methods for Energy Management PTDC/CCI-COM/31198/2017 Researcher Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal	Fundação para a Ciência e a Tecnologia Ongoing
2017/07 - 2019/12/31	BioData 22231 Researcher Universidade de Lisboa Instituto Superior Técnico, Portugal	Fundação para a Ciência e a Tecnologia
2014/01 - 2015/05	GEN6: Governments Enabled with IPv6 ? Researcher Universidade de Lisboa Instituto Superior Técnico, Portugal	European Union Concluded
2010/04/04 - 2013/10/03	ParSAT: Parallel Satisfiability Algorithms and Its Applications PTDC/EIA-EIA/103532/2008 Researcher Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal	Fundação para a Ciência e a Tecnologia Concluded
2005/01 - 2008/06	PowerPlan: Power Planning in Electronic Systems POSC/EEA-ESE/61528/2004 Researcher Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal	Fundação para a Ciência e a Tecnologia
1997/12 - 2000/12	VerIC: Modelling, Characterization and Verification of Digital Circuits 2/2.1/TIT/1639/95 Researcher Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal	Fundação para a Ciência e a Tecnologia Concluded

Contract

	Designation	Funders
2014/01 - 2015/06	MAPIST: Modernização Administrativa dos Processos do IST 23283 Coordinator for IT-related activities and tasks Universidade de Lisboa Instituto Superior Técnico, Portugal	Agência para a Modernização Administrativa Concluded
1996/03 - 2012/12	Lisbon Center of the Cadence Research Laboratories ? Researcher Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal	Cadence Design Systems Inc Concluded

Publications

Book chapter	Silva, Luis Guerra e; Zhu, Zhenhai; Phillips, Joel R.; Silveira, L. Miguel. "Library Compatible Variational Delay Computation". In IFIP International Federation for Information Processing, 157-176. Springer US, 2006. Published • 10.1007/978-0-387-74909-9_10 Visweswariah, Chandu; Conn, Andrew R.; Silva, Luís G.. "Exploiting Optimality Conditions in Accurate Static Circuit Tuning". In High Performance Algorithms and Software for Nonlinear Optimization, 363-381. Springer US, 2003. Published • 10.1007/978-1-4613-0241-4_17
Conference paper	Ricardo Barata; Sérgio Silva; Luís Cruz; Silva, Luís. "Open APIs in Information Systems for Higher Education". Paper presented in European University Information Systems Conference (EUNIS), Umea, 2014. Published Marques, R.; Guerra E Silva, L.; Flores, P.; Silveira, L.M.. "Improving SAT Solver Efficiency Using a Multi-Core Approach". Paper presented in International Florida Artificial Intelligence Research Society Conference (FLAIRS), 2013. Published Sinha, D.; Guerra E Silva, L.; Wang, J.; Raghunathan, S.; Netrabile, D.; Shebaita, A.. "TAU 2013 Variation Aware Timing Analysis Contest". Paper presented in ACM International Symposium on Physical Design (ISPD), The Ridge Tahoe, Stateline, NV, 2013. Published • 10.1145/2451916.2451960 Guerra e Silva, Luis. "Unifying Functional and Parametric Timing Verification". Paper presented in ACM Great Lakes Symposium on VLSI (GLVLSI), Salt Lake City, UT, 2012. Published • 10.1145/2206781.2206816 Guerra E Silva, L.; Silveira, L.M.. "Handling Intra-Die Variations in PSTA". Paper presented in ACM Great Lakes Symposium on VLSI (GLSVLSI), Lausanne, 2011. Published • 10.1145/1973009.1973094 E Silva, L.G.; Phillips, J.R.; Miguel Silveira, L.. "Speedpath Analysis Under Parametric Timing Models". Paper presented in Design Automation Conference (DAC), Anaheim, CA, 2010. Published • 10.1145/1837274.1837343 Guerra e Silva, L.; Miguel Silveira, L.; Phillips, J.R.. "Efficient Computation of the Worst-Delay Corner". Paper presented in IEEE/ACM Design, Automation and Test in Europe Conference (DATE), Nice, 2007. Published • 10.1109/DATE.2007.364533 Silva, Luís; Philips, Joel R; Luís Miguel Teixeira D'Ávila Pinto da Silveira. "Efficient Computation of the Exact Worst-Delay Corner". Paper presented in IEEE/ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU),, Austin, TX, 2007. Published E Silva, Luis; Zhu, Zhenhai; Phillips, Joel; Silveira, L.. "Variation-Aware, Library Compatible Delay Modeling Strategy". Paper presented in IFIP International Conference on Very Large Scale Integration, Nice, 2006. Published • 10.1109/vlsisoc.2006.313215 João Marques-Silva; Silva, Luís. "Algorithms for Satisfiability in Combinational Circuits Based on Backtrack Search and Recursive Learning". Paper presented in XII Symposium on Integrated Circuits and Systems Design (SBCCI), Natal, 2002. Published João Marques-Silva; Silva, Luís. "Algorithms for Satisfiability in Combinational Circuits Based on Backtrack Search and Recursive Learning". Paper presented in IEEE/ACM International Workshop on Logic Synthesis (IWLS), Lake Tahoe, CA, 1999. Guerra e Silva, L.; Marques-Silva, J.; Silveira, L.M.. "Algorithms for Solving Boolean Satisfiability in Combinational Circuits". Paper presented in IEEE/ACM Design Automation Conference (DATE), Munich, 1999. Published • 10.1109/date.1999.761177 Silva, L.G.; Silva, J.M.; Silveira, L.M.; Skallah, K.A.. "Timing analysis using propositional satisfiability". Paper presented in IEEE International Conference on Electronic, Circuits and Systems, Lisboa, 1998. Published • 10.1109/icecs.1998.813943 e Silva, L.G.; Marques Silva, J.P.; Silveira, L.M.; Sakallah, K.A.. "Realistic Delay Modeling in Satisfiability-Based Timing Analysis". Paper presented in IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, 1998. Published • 10.1109/iscas.1998.705250 Silva, Luís; João Marques-Silva; L. Miguel Silveira; Karem A. Sakallah. "Satisfiability Models and Algorithms for Circuit Delay Computation". Paper presented in ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Austin, TX, 1997. Published
Journal article	e Silva, Luis Guerra; Phillips, Joel; Silveira, L. Miguel. "Effective Corner-Based Techniques for Variation-Aware IC Timing Verification". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29 1 (2010): 157-162. http://dx.doi.org/10.1109/tcad.2009.2034343. Published • 10.1109/tcad.2009.2034343 Silva, L.G.; Zhu, Z.; Phillips, J.R.; Silveira, L.M.. "Library Compatible Variational Delay Computation". IFIP International Federation for Information Processing 249 (2008): 157-176. http://www.scopus.com/inward/record.url?eid=2-s2.0-36448940173&partnerID=MN8TOARS. 10.1007/978-0-387-74909-9_10 Marques-Silva, J.; Guerra e Silva, L.. "Solving Satisfiability in Combinational Circuits". IEEE Design & Test of Computers 20 4 (2003): 16-21. http://dx.doi.org/10.1109/mdt.2003.1214348. Published • 10.1109/mdt.2003.1214348 Guerra e Silva, Luís; Marques-Silva, João; Silveira, L. Miguel; Sakallah, Karem A.. "Satisfiability Models and Algorithms for Circuit Delay Computation". ACM Transactions on Design Automation of Electronic Systems (TODAES) 7 1 (2002): 137-158. http://dx.doi.org/10.1145/504914.504920. 10.1145/504914.504920

Intellectual property

Patent

Silva, Luís; L. Miguel Silveira; Joel Phillips. 2012. "Branch and Bound Techniques for Computation of Critical Timing Conditions". United States. Granted/Issued

Award

2013	Bronze Medal (3rd place) - Parallel SAT Solvers Track SAT Competition 2013, Finland
2006	Invention of the Year Cadence Design Systems Inc, United States
2006	Best Paper Award International Conference on Very Large Scale Integration, France