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Identification

Personal identification

Full name
Valeri Skliarov

Citation names

  • Skliarov, Valeri

Author identifiers

Ciência ID
A014-8ED5-1985
ORCID iD
0000-0003-0349-8329
Affiliation

Teaching in Higher Education

Category
Host institution 		Employer
2013 - 2019 Full Professor (University Teacher) Universidade de Aveiro, Portugal
Outputs

Publications

Book
  1. Sklyarov, V.. Embedded blocks and system-level design. 2014.
    10.1007/978-3-319-04708-9_4
  2. Sklyarov, V.. Design technique based on hierarchical and parallel specifications. 2014.
    10.1007/978-3-319-04708-9_5
  3. Sklyarov, V.; Skliarova, I.. High-performance data processing over N-ary trees. 2014.
    10.1007/978-1-4614-1791-0_8
Conference paper
  1. Sklyarov, V.; Skliarova, I.; Silva, J.; Sudnitson, A.; Rjabov, A.. "Hardware accelerators for information retrieval and data mining". 2015.
    10.1109/ICTRC.2015.7156457
  2. Skliarova, I.; Sklyarov, V.; Rjabov, A.; Sundnitson, A.. "Hardware/software co-design in extensible processing platforms for combinatorial search algorithms". 2014.
    10.1109/MELCON.2014.6820578
  3. Sklyarov, V.; Skliarova, I.; Silva, J.; Sudnitson, A.. "Design space exploration in multi-level computing systems". 2014.
    10.1145/2659532.2659616
  4. Skliarova, I.; Sklyarov, V.; Sudnitson, A.; Kruus, M.. "Teaching FPGA-based systems". 2014.
    10.1109/EDUCON.2014.6826133
  5. Sklyarov, V.; Skliarova, I.. "Programmable systems-on-chip for information processing". 2014.
    10.1109/ICAICT.2014.7035967
  6. Sklyarov, V.; Skliarova, I.; Silva, J.; Rjabov, A.; Sudnitson, A.. "Application of extensible processing platforms for experiments with FPGA-based circuits". 2014.
    10.1109/MELCON.2014.6820579
  7. Mihhailov, D.; Sudnitson, A.; Sklyarov, V.; Skliarova, I.. "Implementation of address-based data sorting on different FPGA platforms". 2013.
    10.1109/EWDTS.2013.6673195
  8. Sklyarov, V.; Skliarova, I.; Kruus, M.; Mihhailov, D.; Sudnitson, A.. "Address-based data processing over N-ary trees". 2013.
    10.1109/EUROCON.2013.6625220
  9. Mihhailov, D.; Rjabov, A.; Sklyarov, V.; Skliarova, I.; Sudnitson, A.. "Optimization of address-based data sorting unit with external memory support". 2013.
    10.1145/2516775.2516807
Journal article
  1. Sklyarov, V.; Skliarova, I.; Rjabov, A.; Sudnitson, A.. "Zynq-based system for extracting sorted subsets from large data sets". Informacije MIDEM 45 2 (2015): 142-152. http://www.scopus.com/inward/record.url?eid=2-s2.0-84936950558&partnerID=MN8TOARS.
  2. Silva, J.; Sklyarov, V.; Skliarova, I.. "Comparison of On-chip Communications in Zynq-7000 All Programmable Systems-on-Chip". IEEE Embedded Systems Letters 7 1 (2015): 31-34. http://www.scopus.com/inward/record.url?eid=2-s2.0-84924331822&partnerID=MN8TOARS.
    10.1109/LES.2015.2399656
  3. Sklyarov, V.; Skliarova, I.. "Design and implementation of counting networks". Computing 97 6 (2015): 557-577. http://www.scopus.com/inward/record.url?eid=2-s2.0-84929321472&partnerID=MN8TOARS.
    10.1007/s00607-013-0360-y
  4. Sklyarov, V.; Skliarova, I.. "Multi-core DSP-based vector set bits counters/comparators". Journal of Signal Processing Systems 80 3 (2015): 309-322. http://www.scopus.com/inward/record.url?eid=2-s2.0-84928376304&partnerID=MN8TOARS.
    10.1007/s11265-014-0915-y
  5. Rjabov, A.; Sklyarov, V.; Skliarova, I.; Sudnitson, A.. "Processing sorted subsets in a multi-level reconfigurable computing system". Elektronika ir Elektrotechnika 21 2 (2015): 30-33. http://www.scopus.com/inward/record.url?eid=2-s2.0-84928680168&partnerID=MN8TOARS.
    10.5755/j01.eee.21.2.11509
  6. Sklyarov, V.; Skliarova, I.. "High-performance implementation of regular and easily scalable sorting networks on an FPGA". Microprocessors and Microsystems 38 5 (2014): 470-484. http://www.scopus.com/inward/record.url?eid=2-s2.0-84903318125&partnerID=MN8TOARS.
    10.1016/j.micpro.2014.03.003
  7. Sklyarov, V.; Skliarova, I.. "Hamming weight counters and comparators based on embedded DSP blocks for implementation in FPGA". Advances in Electrical and Computer Engineering 14 2 (2014): 63-68. http://www.scopus.com/inward/record.url?eid=2-s2.0-84901843912&partnerID=MN8TOARS.
    10.4316/AECE.2014.02011
  8. Sklyarov, V.; Skliarova, I.; Rjabov, A.; Sudnitson, A.. "Fast matrix covering in all programmable systems-on-chip". Elektronika ir Elektrotechnika 20 5 (2014): 150-153. http://www.scopus.com/inward/record.url?eid=2-s2.0-84901019834&partnerID=MN8TOARS.
    10.5755/j01.eee.20.5.7116
  9. Silva, Valter; Santos, Frederico; Skliarov, Valeri. "A interligação do Visual C++ com as FPGAs da Xilinx". (2000): http://hdl.handle.net/10773/7037.
Thesis / Dissertation
  1. Marques, Vítor Manuel dos Santos. "Performance of hardware and software sorting algorithms implemented in a SOC". Master, 2017. http://hdl.handle.net/10773/23467.
  2. Oliveira, Ramiro Manuel Silva. "Análise e comparação de métodos soft/hard em sistemas reconfiguráveis". Master, 2010. http://hdl.handle.net/10773/3709.
  3. Figueiredo, Luís Carlos Nobre de Almeida. "Implementação em FPGA de algoritmos computacionais paralelos". Master, 2010. http://hdl.handle.net/10773/3567.
  4. Serra, Carlos David Alexandre. "Análise e implementação de ordenação de dados em FPGA". Master, 2010. http://hdl.handle.net/10773/4484.
  5. Lima, João Filipe Fernandes Garcia. "Processador com conjunto de instruções variável remotamente". Master, 2009. http://hdl.handle.net/10773/2188.
  6. Sousa, Rui Miguel Teixeira de. "Biblioteca para a comunicação entre FPGA e dispositivos periféricos". Master, 2009. http://hdl.handle.net/10773/2146.
  7. Neves, Abílio Paulo Pinho. "Interacção remota com circuitos implementados em FPGA". Master, 2009. http://hdl.handle.net/10773/2189.
  8. Soldado, Sérgio Torres. "FPGA urban traffic control simulation and evaluation platform". Master, 2009. http://hdl.handle.net/10773/2190.
  9. Pimentel, Bruno Figueiredo. "Synthesis of FPGA-based accelerators implementing recursive algorithms". PhD, 2009. http://hdl.handle.net/10773/2226.
  10. Oliveira, Arnaldo Silva Rodrigues de. "Especialização e síntese de processadores para aplicação em sistemas de tempo-real". PhD, 2007. http://hdl.handle.net/10773/4669.
  11. Melo, Andreia Barbosa de. "Uma metodologia para especificação e síntese de unidades de controlo reconfiguráveis". PhD, 2006. http://hdl.handle.net/10773/2208.