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I received my M.Sc. degree in the field of Computer System Architecture, Computer Engineering from Shahid Beheshti University, Tehran, Iran. My research interests are computer arithmetic, computer architecture, and machine learning. I am a researcher at INESC-ID and currently, I am working on hardware accelerators using computer arithmetic designs for machine learning applications.
Identification

Personal identification

Full name
Sahar Moradi Cherati

Citation names

  • Cherati, Sahar

Author identifiers

Ciência ID
9010-A18F-D232
ORCID iD
0000-0002-9914-501X
Education
Degree Classification
2027/03
Ongoing
 Electrical and Computer Engineering (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016/09/22 - 2019/03/03
Concluded
 Computer Systems Architecture (Master)
Major in Computer Engineering
Shahid Beheshti University, Iran
"Modulo-(2n+3) Parallel Prefix Addition via Diminished-3 Representation of Residues" (THESIS/DISSERTATION)
 17.72
2009/09/22 - 2013/09/22
Concluded
 Hardware (Bachelor)
Major in Computer Engineering
Babol Noshirvani University of Technology, Iran
"Survey on Malicious Software" (THESIS/DISSERTATION)
 15.64
Affiliation

Science

Category
Host institution 		Employer
2021/10/11 - Current Researcher (Research) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Outputs

Publications

Conference paper
  1. Jaberipur, Ghassem; Moradi Cherati, Sahar. "Modulo-(2n+3) Parallel Prefix Addition via Diminished-3 Representation of Residues". Paper presented in IEEE international Symposium on Computer Arithmetic (ARITH), Kyoto, 2019.
    Published • 10.1109/arith.2019.00035
Activities

Course / Discipline taught

Academic session Degree Subject (Type) Institution / Organization
2022 - 2022 Teacher Assistant High Performance Computer Architecture Laboratory (Bacharelato) Universidade de Lisboa Instituto Superior Técnico, Portugal
2018 - 2019 Teacher Assistant Logical Circuits (Bachelor) Shahid Beheshti University, Iran
2018/02 - 2018/08 Teacher Assistant Logical Circuits and Computer Architecture Laboratory (Bachelor) Shahid Beheshti University, Iran
2018 - 2018 Teacher Assistant VHDL Programming Language (Master) Shahid Beheshti University, Iran
2017 - 2018 Teacher Assistant Computer Arithmetic and Advanced Computer Arithmetic (Master) Shahid Beheshti University, Iran
2017 - 2017 Teacher Assistant Microprocessor (Bachelor) Shahid Beheshti University, Iran
2016 - 2017 Teacher Assistant Data communication (Bachelor) Shahid Beheshti University, Iran
2012 - 2013 Teacher Assistant Digital Electronic (Bachelor) Babol Noshirvani University of Technology, Iran

Other jury / evaluation

Activity description Institution / Organization
2022 - Current Reviewer of IEEE International Symposium on Circuits and Systems (ISCAS 2022, ISCAS 2023, ISCAS 2024)
2021 - Current Reviewer of Journal of Signal Processing Systems Springer
2024 - 2024 Reviewer of 34th International Conference on Field-Programmable Logic and Applications (FPL 2024)
2023 - 2023 Reviewer of Job Scheduling Strategies for Parallel Processing (JSSPP 2023)
2023 - 2023 Reviewer of 34th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2023)
2023 - 2023 Reviewer of 30th IEEE Symposium on Computer Arithmetic - ARITH 2023
2023 - 2023 Reviewer of IEEE International Conference on Multimedia Big Data (BigMM 2023)
2022 - 2023 Reviewer of Euromicro Conference on Digital Systems Design (DSD2022-DSD2023)
2021 - 2021 Reviewer of The 19th IEEE International Symposium on Parallel and Distributed Processing with Applications (IEEE ISPA 2021)
Distinctions

Award

2023 PhD studentship
Universidade de Lisboa Instituto Superior Técnico, Portugal
2021 Research grant
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal