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MÁRIO PEREIRA VESTIAS completed his Ph.D. in Electrical and Computer Engineering in 2002/07 at Instituto Superior Técnico, his master’s in electrical and computer engineering in 1996/12 at Instituto Superior Técnico, a degree in Electrical and Computer Engineering in 1993/06 at Instituto Superior Técnico and a second degree in Technological Physics Engineering in 1996/07 at Instituto Superior Técnico. He has been a Researcher at the Institute of Systems and Computer Engineering Research and Development in Lisbon since 1998 and a Coordinator Professor at the Polytechnic Institute of Lisbon, Instituto Superior de Engenharia de Lisboa. He has published 33 articles in specialized journals, 17 book chapters, and 77 papers in international conferences. He is supervising 1 doctoral thesis(s) and 8 master thesis. He is(was) involved in 27 research projects, 5 of them as principal investigator. He works in the area(s) of Engineering Sciences and Technologies, with a major focus on high-performance embedded computing architectures for deep learning, SAR, and hyperspectral processing, among others.
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Identification

Personal identification

Full name
MÁRIO PEREIRA VÉSTIAS

Citation names

  • VÉSTIAS, MÁRIO

Author identifiers

Ciência ID
4717-C2C7-3F2C
ORCID iD
0000-0001-8556-4507

Languages

Language Speaking Reading Writing Listening Peer-review
English Advanced (C1) Advanced (C1) Advanced (C1) Advanced (C1)
Education
Degree Classification
2002/07
Concluded
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
1996/12
Concluded
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
1996/07
Concluded
 Ciências de Engenharia - Engenharia Física Tecnológica (Licenciatura)
Universidade de Lisboa Instituto Superior Técnico, Portugal
1988/09/15 - 1993/06/30
Concluded
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Licenciatura)
Universidade de Lisboa Instituto Superior Técnico, Portugal
Projects

Contract

Designation Funders
2019 - 2021 PEPCC - Power Efficiency and Performance for Embedded and HPC Systems with Custom CGRAs
Ref.
Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
2019 - 2020 Optimization of Convolutional Neural Networks in FPGA using Incremental Inference
IPL/IDI&CA/2019/InCNeuralN/ISEL
Principal investigator
Instituto Politécnico de Lisboa, Portugal
 Instituto Politécnico de Lisboa
Ongoing
2018 - 2019 LiteCNN - Implementing Convolutional Neural Networks in FPGA for Embedded Systems
IPL/IDI&CA/2018/LiteCNN/ISEL
Principal investigator
Instituto Politécnico de Lisboa, Portugal
 Instituto Politécnico de Lisboa
Concluded
2011 - 2013 REAGE Experimental Receiver Galileo for Space Usage
REAGE-DME-PMD-PRE01-E
Researcher
Instituto Politécnico de Lisboa Grupo de Investigação em Electrónica de Sistemas e de Telecomunicações, Portugal
2011 - 2012 Fibers & Photons
FIBRAS e FOTÕES
Researcher
Instituto Politécnico de Lisboa Área Departamental de Engenharia de Electrónica e Telecomunicações e de Computadores, Portugal
 Fundação Calouste Gulbenkian
2009 - 2011 Sideworks
Projeto QREN
Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Concluded
2009 - 2011 UWB Receiver: baseband processing using reconfigurable Hardware
PTDC/EEAELC/67993/2006
Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
2007/10/01 - 2011 Reconfigurable Hardware using Magnetic Tunneling Junction Memories
PTDC/EEA-ELC/72933/2006
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
2007/11/01 - 2010/02/28 Receptor de UWB: processamento de banda de base usando hardware reconfigurável
PTDC/EEA-ELC/67993/2006
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2007 - 2009 COBAYA: CLOSING THE COMPILATION GAP BETWEEN ALGORITHMS AND COARSE-GRAINED RECONFIGURABLE ARRAY ARCHITECTURES
PTDC/EEA-ELC/70272/2006
Researcher
Fundação para a Ciência e a Tecnologia
Concluded
1997/04/01 - 2001/03/31 PROJECTO DE SISTEMAS EMBEBIDOS HARDWARE-SOFTWARE
PRAXIS XXI/BD/11391/97
 Fundação para a Ciência e a Tecnologia
Concluded
1998 - 1999 Circuits of Polycristaline Silicon Deposited at Low Temperature for Electronics of High Areas - POLY-IC
PRAXIS/3/3.1/MMA/1775/95
Research Fellow
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
1995 - 1997 Euro-Lasic; Rapid Prototyping of Digital, Analogic and Mixed Integrated Circuits
PRAXIS/2/2.1/TIT/1643/95
Research Fellow
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
1994/10/01 - 1996/06/30 Development of algorithms and Computational Tools to Design Electronic Systems
PRAXIS XXI/BM/585/94
 Fundação para a Ciência e a Tecnologia
Concluded
1993 - 1995 QuickChips
ESPRIT - QuickChips
Integration into Research Grant Fellow
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Outputs

Publications

Book
  1. Redes Cisco para Profissionais. Lisboa, Portugal: FCA – Editora de Informática. 2016.
    Published
  2. Redes Cisco para Profissionais. Lisboa, Portugal: FCA – Editora de Informática. 2009.
    Published
  3. Redes Cisco para Profissionais. Lisboa, Portugal: FCA – Editora de Informática. 2006.
    Published
Book chapter
  1. Mário Pereira Véstias. "Convolutional Neural Network". 2022.
    Published • 10.4018/978-1-6684-2408-7.ch077
  2. Mário P. Véstias. "Deep Learning on Edge". In Challenges and Trends. 2022.
    Published • 10.4018/978-1-6684-5700-9.ch007
  3. Mário Pereira Véstias. "Convolutional Neural Network". 12-26. {IGI, 2021.
    Published • 10.4018/978-1-7998-3479-3.ch002
  4. Mário Pereira Véstias. "High-Speed Viterbi Decoder". 245-256. {IGI, 2021.
    Published • 10.4018/978-1-7998-3479-3.ch019
  5. Mário Pereira Véstias. "Field-Programmable Gate Array". 257-270. {IGI, 2021.
    Published • 10.4018/978-1-7998-3479-3.ch020
  6. Véstias, Mário P.. "Deep Learning on Edge". In Advances in Computational Intelligence and Robotics, 23-42. IGI Global, 2020.
    Published • 10.4018/978-1-7998-2112-0.ch002
  7. Mário, Valter; Lopes, João D.; Véstias, Mário; de Sousa, José T.. "Implementing CNNs Using a Linear Array of Full Mesh CGRAs". In Applied Reconfigurable Computing. Architectures, Tools, and Applications, 288-297. Springer International Publishing, 2020.
    Published • 10.1007/978-3-030-44534-8_22
  8. Véstias, Mário. "Processing Systems for Deep Learning Inference on Edge Devices". In Convergence of Artificial Intelligence and the Internet of Things, 213-240. Springer International Publishing, 2020.
    10.1007/978-3-030-44907-0_9
  9. Gonçalves, Ana; Peres, Tiago; Véstias, Mário. "Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs". In Lecture Notes in Computer Science, 387-401. Springer International Publishing, 2019.
    Published • 10.1007/978-3-030-17227-5_27
  10. VÉSTIAS, MÁRIO. "Viterbi Decoder in Hardware". In Advanced Methodologies and Technologies in Network Architecture, Mobile Computing, and Data Analytics. IGIGlobal, 2019.
    Published
  11. VÉSTIAS, MÁRIO. "High-Performance Reconfigurable Computing". In Advanced Methodologies and Technologies in Network Architecture, Mobile Computing, and Data Analytics. IGIGlobal, 2019.
    Published
  12. Mário Pereira Vestias. "Decimal Hardware Multiplier". 722-736. {IGI, 2019.
    Published • 10.4018/978-1-5225-7368-5.ch054
  13. Mário Pereira Vestias. "Adaptive Networks for On-Chip Communication". 655-666. {IGI, 2019.
    Published • 10.4018/978-1-5225-7368-5.ch049
  14. Mário Pereira Véstias. "Viterbi Decoder in Hardware". 6307-6318. {IGI, 2018.
    Published • 10.4018/978-1-5225-2255-3.ch549
  15. Mário Pereira Vestias. "High-Performance Reconfigurable Computing". 4018-4029. {IGI, 2018.
    10.4018/978-1-5225-2255-3.ch348
  16. Mário Pereira Vestias. "Decimal Hardware Multiplier". 4607-4618. {IGI, 2018.
    Published • 10.4018/978-1-5225-2255-3.ch400
  17. Mário Pereira Vestias. "Adaptive Networks for On-Chip Communication". 4549-4559. {IGI, 2018.
    Published • 10.4018/978-1-5225-2255-3.ch395
  18. VÉSTIAS, MÁRIO. "Adaptive Networks for on-Chip Communication". In Encyclopedia of Information Science and Technology. 2017.
  19. VÉSTIAS, MÁRIO. "Decimal Multiplication". In Encyclopedia of Information Science and Technology,. IGIGlobal, 2014.
    Published
  20. VÉSTIAS, MÁRIO. "Adaptive Networks-on-Chip". In Encyclopedia of Information Science and Technology. IGIGlobal, 2014.
    Published
  21. VÉSTIAS, MÁRIO. "High-Performance Reconfigurable Computing: Granularity". In Encyclopedia of Information Science and Technology. IGIGlobal, 2014.
    Published
  22. VÉSTIAS, MÁRIO; Horácio C. Neto. "Decimal Division using the Newton-Raphson Method and Radix-1000 Arithmetic". In Embedded Systems Design with FPGAs. Springer, 2013.
    Published
  23. VÉSTIAS, MÁRIO; Horário C. Neto. "Dynamically Reconfigurable Networks-on-Chip using Runtime Adaptive Routers". In Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication. IGI Global, 2010.
Conference paper
  1. P. Lourenço; M. Véstias; A. Fantoni; M. Vieira. "Multimode interference reflectors and output tuning using neural networks". Paper presented in SPIE West, 2024.
    Published
  2. G. Galvão; A. Vieira; M. Vieira; M. Véstias; P. Vieira; P. Louro. "Traffic signals and cooperative trajectories at urban intersections: leveraging visible light communication for implementation". Paper presented in SPIE West, 2024.
    Published
  3. R. Fernandes; M. A. Vieira; M. Vieira; P. Vieira; P. Louro; M. Véstias. "Using visible light communication to implement intelligent traffic signals and cooperative trajectories at urban intersections". Paper presented in 9th International Conference on Sensors and Electronic Instrumentation Advances (SEIA' 2023), 2023.
    Published
  4. Gonçalo Galvão; Manuel Vieira; Manuela Vieira; Paula Louro; Mário Véstias; Pedro Vieira. "Visible Light Communication at Urban Intersections to Improve Traffic Signaling and Cooperative Trajectories". Paper presented in 2023 International Young Engineers Forum (YEF-ECE), 2023.
    Published
  5. VÉSTIAS, MÁRIO; César Gouveia; Rui Policarpo Duarte; Cláudio de Campos Neto, Horácio. "FPGA-Based Traffic-Sign Classification using CNNs". Paper presented in Jornadas sobre Sistemas Reconfiguráveis, 2020.
    Published
  6. VÉSTIAS, MÁRIO; Rui Policarpo Duarte; José T. de Sousa; Cláudio de Campos Neto, Horácio. "Redes Neuronais Convolucionais em FPGA de Baixa Densidade". Paper presented in Jornadas sobre Sistemas Reconfiguráveis, 2020.
    Published
  7. Mário, Valter; Lopes, João D.; Véstias, Mário; De Sousa, Jose. "Implementing CNNs using a linear array of full mesh CGRAs". 2020.
  8. Fiolhais, Luis; Goncalves, Fernando; Duarte, Rui P.; Vestias, Mario; de Sousa, Jose T.. "Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores". Paper presented in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019.
    Published • 10.1109/iscas.2019.8702538
  9. VÉSTIAS, MÁRIO; Ana Gonçalves; Tiago Peres. "Exploring Data Bitwidth to Run Convolutional Neural Networks in Low Density FPGAs". 2019.
    Published
  10. Vestias, Mario P.; Policarpo Duarte, Rui; de Sousa, Jose T.; Neto, Horacio. "Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA". 2019.
    Published • 10.1109/fpl.2019.00062
  11. Peres, Tiago; Gonçalves, Ana; Véstias, Mário. "Faster convolutional neural networks in low density FPGAs using block pruning". 2019.
    https://doi.org/10.1007/978-3-030-17227-5_28
  12. Nascimento, José M. P.; Vestias, Mario. "Hyperspectral compressive sensing: a comparison of embedded GPU and ARM implementations". 2019.
    Published • 10.1117/12.2532581
  13. VÉSTIAS, MÁRIO; José Nascimento. "Low Power Compressive Sensing for Hyperspectral Imagery". Paper presented in Conference on Telecommunications, 2019.
    Published
  14. VÉSTIAS, MÁRIO; Ana Gonçalves; Tiago Peres. "Otimização de Redes Neuronais Convolucionais em FPGA com Redução do Tamanho dos Operandos". Paper presented in Jornadas sobre Sistemas Reconfiguráveis, 2019.
    Published
  15. VÉSTIAS, MÁRIO; Tiago Peres; Ana Gonçalves. "Otimização de Redes Neuronais Convolucionais em FPGA com Redução do Número de Pesos". Paper presented in Jornadas sobre Sistemas Reconfiguráveis, 2019.
    Published
  16. Gonçalves, Ana; Peres, Tiago; Véstias, Mário. "Exploring data size to run convolutional neural networks in low density FPGAs". 2019.
    https://doi.org/10.1007/978-3-030-17227-5_27
  17. Nascimento, Jose; Véstias, Mário; Duarte, Rui. "Hyperspectral compressive sensing - a low power consumption approach". 2018.
    10.1117/12.2326118
  18. VÉSTIAS, MÁRIO; Rui P. Duarte. "Rapid Prototyping of Approximate Signal Processing Using Stochastic Processors on FPGAs". Paper presented in DASIP, 2018.
    Published
  19. Véstias, Mário; Duarte, Rui; De Sousa, Jose; Cláudio de Campos Neto, Horácio. "Parallel dot-products for deep learning on FPGA". 2017.
    10.23919/FPL.2017.8056863
  20. Lopes, Joao D.; de Sousa, Jose T.; Neto, Horacio; Vestias, Mario. "K-means clustering on CGRA". 2017.
    Published • 10.23919/fpl.2017.8056854
  21. VÉSTIAS, MÁRIO; Rui P. Duarte; Horácio C. Neto. "On the Computation of Approximation Coefficients in ROM-based Redundancy for SEU Mitigation on FPGAs". Paper presented in Workshop on Reliable Field Programmable Logic, 2017.
  22. Duarte, Rui Policarpo; Neto, Horácio; Véstias, Mário. "XtokaxtikoX: a stochastic computing-based autonomous cyber-physical system". 2016.
    10.1109/ICRC.2016.7738716
  23. VÉSTIAS, MÁRIO. "Multiband Ultra-Wideband Receiver Implementation in a Low Cost FPGA". Paper presented in LASCAS, 2016.
  24. Pinhão, João; José, Wilson; Neto, Horácio; Véstias, Mário. "Sparse matrix multiplication on a reconfigurable many-core architecture". 2015.
    10.1109/DSD.2015.89
  25. Nascimento, José M. P.; Véstias, Mário; Martin, Gabriel. "FPGA-based architecture for hyperspectral unmixing". 2015.
    10.1109/IGARSS.2015.7326130
  26. José, Wilson; Neto, Horácio; Véstias, Mário. "A many-core co-processor for embedded parallel computing on FPGA". 2015.
    10.1109/DSD.2015.23
  27. Rodrigues, Tiago; Véstias, Mário. "Using dynamic reconfiguration to reduce the area of a JPEG decoder on FPGA". 2015.
    10.1109/DSD.2015.31
  28. VÉSTIAS, MÁRIO; Rui P. Duarte; Horácio C. Neto. "Designing Hardware/Software Systems for Embedded High-Performance Computing". Paper presented in FPGAs for Software Programmers, 2015.
    Published
  29. VÉSTIAS, MÁRIO; Rui P. Duarte; Horácio C. Neto. "Enhancing Stochastic Computations via Process Variation". Paper presented in Field Programmable Logic and Applications, 2015.
    Published
  30. VÉSTIAS, MÁRIO; João Rosário; José P. Nascimento. "FPGA-based Architecture for Hyperspectral Unmixing". Paper presented in IEEE Geoscience and Remote Sensing Society, 2015.
    Published • 10.1109/whispers.2016.8071765
  31. Vestias, Mario; Neto, Horacio. "Trends of CPU, GPU and FPGA for high-performance computing". Paper presented in Field Programmable Logic and Applications, 2014.
    Published • 10.1109/fpl.2014.6927483
  32. José, Wilson; Silva, Ana Rita; Neto, Horácio; Véstias, Mário. "Efficient Implementation Of A Single-Precision Floating-Point Arithmetic Unit on FPGA". Paper presented in Field Programmable Logic and Applications, 2014.
    10.1109/FPL.2014.6927391
  33. Véstias, Mário; Neto, Horácio. "A many-core overlay for high performance embedded computing on FPGAS". 2014.
  34. Rosário, João; Nascimento, José M. P.; Véstias, Mário. "FPGA-based architecture for hyperspectral endmember extraction". 2014.
    10.1117/12.2067039
  35. José, W.; Silva, A.R.; Véstias, M.; Neto, H.. "Design of a massively parallel computing architecture for dense matrix multiplication". Paper presented in 2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013 - Conference Proceedings, 2013.
    Published • 10.1109/LASCAS.2013.6519064
  36. Véstias, M.; Neto, H.; Sarmento, H.. "Design of a multiband full-rate ultra-wideband receiver in FPGA". Paper presented in 2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013 - Conference Proceedings, 2013.
    Published • 10.1109/LASCAS.2013.6519066
  37. VÉSTIAS, MÁRIO. "Very low resource table-based FPGA evaluation of elementary functions". Paper presented in International Conference on Reconfigurable Computing and FPGAs, 2013.
    Published
  38. VÉSTIAS, MÁRIO; José, Wilson M.; Ana rita silva; Neto, Horácio C.. "Analysis of Matrix Multiplication on High Density Virtex-7 FPGA". Paper presented in Field Programmable Logic and Applications, 2013.
    Published
  39. VÉSTIAS, MÁRIO; Vitor Silva; Jorge Fernandes; Neto, Horácio C.. "A Reconfigurable Computing Architecture using Magnetic Tunneling Junction Memories". Paper presented in Field Programmable Logic and Applications, 2013.
    Published
  40. Vestias, M.; Neto, H.; Sarmento, H.. "Design of high-speed viterbi decoders on virtex-6 FPGAs". Paper presented in Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012, 2012.
    Published • 10.1109/DSD.2012.42
  41. Véstias, M.; Neto, H.. "Parallel decimal multipliers and squarers using Karatsuba-Ofman's algorithm". Paper presented in Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012, 2012.
    Published • 10.1109/DSD.2012.101
  42. Silva, V.; Fernandes, J.R.; Vestias, M.P.; Neto, H.C.. "A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory". Paper presented in 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012, 2012.
    10.1109/ReConFig.2012.6416756
  43. Véstias, M.; Sarmento, H.. "Design of an IEEE 802.15.3c baseband processor in FPGA". Paper presented in IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin, 2012.
    Published • 10.1109/ICCE-Berlin.2012.6336503
  44. Véstias, M.; Neto, H.; Sarmento, H.. "Sliding block Viterbi decoders in FPGA". Paper presented in Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012, 2012.
    Published • 10.1109/FPL.2012.6339215
  45. Véstias, M.. "Design and test of a MIMO receiver based on the Alamouti scheme in FPGA". Paper presented in IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin, 2012.
    Published • 10.1109/ICCE-Berlin.2012.6336452
  46. Pinho, Pedro; Véstias, Mário. "A high-rate mimo receiver in an FPGA". Paper presented in IEEE International Symposium on Antennas and Propagation and USNC/URSI National Radio Science Meeting, 2012.
    Published
  47. Véstias, Mário; Sarmento, Helena. "FPGA implementation of IEEE 802.15.3C receiver". Paper presented in IEEE International Symposium on Consumer Electronics, 2012.
    Published
  48. VÉSTIAS, MÁRIO; José, Wilson M.; Cláudio de Campos Neto, Horácio. "Interconnection Networks for Tightly Coupled Processors in FPGA". Paper presented in Conference on Design of Circuits and Integrated Systems, 2012.
    Published
  49. VÉSTIAS, MÁRIO; Vitor Silva; Jorge Fernandes; Cláudio de Campos Neto, Horácio. "Magnetic-Memory based Dynamically Reconfigurable Array". Paper presented in Conference on Design of Circuits and Integrated Systems, 2012.
    Published
  50. VÉSTIAS, MÁRIO; Helena Sarmento. "Tradeoffs in the Design of Sliding Block Viterbi Decoders for MB-OFDM UWB Systems". Paper presented in International Conference in Consumer Electronics, 2012.
    Published
  51. VÉSTIAS, MÁRIO; Helena Sarmento; Cláudio de Campos Neto, Horácio. "Efficient Design of Sliding Block Viterbi Decoders in FPGA". Paper presented in International Conference on Field Programmable Logic Applications, 2012.
    Published
  52. VÉSTIAS, MÁRIO; Cláudio de Campos Neto, Horácio. "Efficient Parallel Decimal Multipliers and Squarers using Karatsuba-Ofman's Algorithm". Paper presented in Digital Systems Design, 2012.
    Published
  53. Silva, Victor; Vestias, Mario P.; Neto, Horacio C.; Fernandes, Jorge R.. "Non-Volane Memory Circuits for FIMS and TAS Writing Techniques on Magnetic Tunnelling Junctions". 2012.
  54. Véstias, M.P.; Neto, H.C.. "Revisiting the Newton-Raphson iterative method for decimal division". Paper presented in Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011, 2011.
    10.1109/FPL.2011.33
  55. Véstias, M.P.; Neto, H.C.. "Iterative decimal multiplication using binary arithmetic". Paper presented in Proceedings of the 2011 7th Southern Conference on Programmable Logic, SPL 2011, 2011.
    10.1109/SPL.2011.5782658
  56. Véstias, M.P.; Neto, H.C.. "A dynamic buffer resize technique for networks-on-chip on FPGA". Paper presented in Proceedings of the 2011 7th Southern Conference on Programmable Logic, SPL 2011, 2011.
    10.1109/SPL.2011.5782653
  57. VÉSTIAS, MÁRIO; Jorge Silva; Pedro Pinho. "Design of the Alamouti Scheme for a MIMO Receiver and its Implementation on an FPGA". Paper presented in 1st international Conference on Electronics, Telecommunications and Computers, 2011.
    Published
  58. VÉSTIAS, MÁRIO; Helena Sarmento. "Implementing High-Speed Viterbi Decoders for MB-OFDM on FPGA". Paper presented in Conference on Design of Circuits and Integrated Systems, 2010.
    Published
  59. VÉSTIAS, MÁRIO; Cláudio de Campos Neto, Horácio. "Parallel Decimal Multipliers using Binary Multipliers". Paper presented in Southern Programmable Logic Conference, 2010.
    Published
  60. VÉSTIAS, MÁRIO; Hugo Santos; Helena Sarmento. "Implementing and testing the FPGA prototype of a DCM demodulator using the Matlab/Simulink". Paper presented in IEEE Latin American Symposium on Circuits and Systems, 2010.
    Published
  61. Vestias, Mario; Santos, Hugo; Sarmento, Helena. "A DCM Demapper for MB-OFDM on FPGA". 2010.
  62. Duarte, R.; Neto, H.; Véstias, M.. "Double-precision Gauss-Jordan algorithm with partial pivoting on FPGAs". Paper presented in 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009, 2009.
    Published • 10.1109/DSD.2009.199
  63. Silva, V.; Oliveira, L.B.; Fernandes, J.R.; Véstias, M.P.; Neto, H.C.. "Run-time reconfigurable array using magnetic RAM". Paper presented in 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009, 2009.
    Published • 10.1109/DSD.2009.198
  64. VÉSTIAS, MÁRIO; Hugo Santos; Cláudio de Campos Neto, Horácio; Helena Sarmento. "Tradeoffs in the Design of a Viterbi Decoder for a MB-OFDM Receiver". Paper presented in Conference on Design of Circuits and Integrated Systems, 2009.
    Published
  65. Neto, H.C.; Vestias, M.P.. "Architectural tradeoffs in the design of barrel shifters for reconfigurable computing". Paper presented in Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL, 2008.
    Published • 10.1109/SPL.2008.4547728
  66. Neto, H.C.; Véstias, M.P.. "Decimal multiplier on FPGA using embedded binary multipliers". Paper presented in Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, 2008.
    Published • 10.1109/FPL.2008.4629931
  67. Véstias, M.P.; Neto, H.C.. "Router design for application specific networks-on-chip on reconfigurable systems". Paper presented in Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL, 2007.
    Published • 10.1109/FPL.2007.4380677
  68. Véstias, M.P.; Neto, H.C.. "Co-synthesis of a configurable SoC platform based on a network on chip architecture". Paper presented in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2006.
    Published
  69. Véstias, M.P.; Neto, H.C.. "Area and performance optimization of a generic network-on-chip architecture". Paper presented in SBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design, 2006.
    Published
  70. Véstias, M.P.; Neto, H.C.. "A generic network-on-chip architecture for reconfigurable systems: Implementation and evaluation". Paper presented in Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL, 2006.
    Published • 10.1109/FPL.2006.311303
  71. Vestias, Mario P.; Neto, Horacio C.. "Co-Synthesis of a Configurable SoC Platform based on a Network on Chip Architecture". 2006.
    10.1109/ASPDAC.2006.1594644
  72. Véstias, Mário. "Metodologia de projecto de SoC configuráveis baseados em redes intra-chip". 2005.
  73. VÉSTIAS, MÁRIO. "A Reconfigurable SoC Platform based on a Network on Chip Architecture with QoS". Paper presented in Conference on Design of Circuits and Integrated Systems, 2005.
    Published
  74. VÉSTIAS, MÁRIO; Cláudio de Campos Neto, Horácio. "Mapping Data Intensive Applications onto Reconfigurable Hardware/Software Architectures". Paper presented in Conference on Design of Circuits and Integrated Systems, 2003.
    Published
  75. VÉSTIAS, MÁRIO; Cláudio de Campos Neto, Horácio. "DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures". Paper presented in Symposium on Integrated Circuits and Systems Design, 2003.
    Published
  76. VÉSTIAS, MÁRIO; Cláudio de Campos Neto, Horácio. "System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures". Paper presented in IEEE International Conference on Rapid System Prototyping, 2002.
    Published
  77. Vestias, MP; Neto, HC. "System-level co-synthesis of dataflow dominated applications on reconfigurable hardware/software architectures". 2002.
    10.1109/IWRSP.2002.1029748
  78. VÉSTIAS, MÁRIO; Cláudio de Campos Neto, Horácio. "CAMUS: A New Co-Design Methodology for Embedded Signal processing Systems". Paper presented in Conference on Design of Circuits and Integrated Systems, 2001.
    Published
  79. VÉSTIAS, MÁRIO; Cláudio de Campos Neto, Horácio. "CAMUS: System-Level Synthesis of Data-Intensive Applications on Dynamically Reconfigurable Hardware/Software Architectures". Paper presented in Proceedings of MESC’2000 a special section of CONTROLO’2000, 2000.
    Published
Journal article
  1. Miguel Reis; Mário Véstias; Horácio Neto. "Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines". ACM Transactions on Reconfigurable Technology and Systems (2024): https://doi.org/10.1145/3615870.
    10.1145/3615870
  2. Miguel Reis; VÉSTIAS, MÁRIO; Cláudio de Campos Neto, Horácio. Corresponding author: VÉSTIAS, MÁRIO. "Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines". ACM Transactions on Reconfigurable Technology and Systems (2024):
    Published
  3. M. A. VIEIRA; G. GALVÃO; M. VIEIRA; M. VÉSTIAS; P. VIEIRA; P. LOURO. "Enhancing Traffic Management through Visible Light Communication-Driven Signaling and Cooperative Trajectories". Sensors & Transducers 263 4 (2023): 58-66.
    Published
  4. Maria Inês Frutuoso; Horácio C. Neto; Mário P. Véstias; Rui Policarpo Duarte. "Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA". Algorithms (2023): https://doi.org/10.3390/a16030141.
    Published • 10.3390/a16030141
  5. Pedro F. Durães; Mário P. Véstias. "Smart Embedded System for Skin Cancer Classification". Future Internet (2023): https://doi.org/10.3390/fi15020052.
    Published • 10.3390/fi15020052
  6. André L. de Sousa; Mário P. Véstias; Horácio C. Neto. "Multi-Model Inference Accelerator for Binary Convolutional Neural Networks". Electronics (2022): https://doi.org/10.3390/electronics11233966.
    Published • 10.3390/electronics11233966
  7. Véstias, Mário; Duarte, Rui P.; de Sousa, José T.; Neto, Horácio. "Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units". ACM Transactions on Reconfigurable Technology and Systems (2022): http://dx.doi.org/10.1145/3546182.
    Published • 10.1145/3546182
  8. Cruz, Helena; Véstias, Mário; Monteiro, José; Neto, Horácio; Duarte, Rui Policarpo. "A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective". Remote Sensing 14 5 (2022): 1258. http://dx.doi.org/10.3390/rs14051258.
    Published • 10.3390/rs14051258
  9. David Mota; Helena Cruz; Pedro R. Miranda; Rui Policarpo Duarte; Jose T. de Sousa; Horacio C. Neto; Mario P. Vestias. "Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA". IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing (2022): 1-1. https://doi.org/10.1109/JSTARS.2022.3169828.
    Published • 10.1109/JSTARS.2022.3169828
  10. D. Lopes, João; Véstias, Mário; Duarte, Rui Policarpo; Neto, Horácio C; De Sousa, Jose. "Coarse-grained reconfigurable computing with the versat architecture". (2021): http://hdl.handle.net/10400.21/13224.
    Published • 10.3390/electronics10060669
  11. Roque, João, V.; Lopes, João D.; Véstias, Mário; De Sousa, Jose. "IOb-Cache: a high-performance configurable open-source cache". (2021): http://hdl.handle.net/10400.21/13814.
    Published • 10.3390/a14080218
  12. Véstias, Mário; Neto, Horácio C. "Decimal multiplication in FPGA with a novel decimal adder/subtractor". (2021): http://hdl.handle.net/10400.21/13833.
    Published • 10.3390/a14070198
  13. Miranda, Pedro R.; Pestana, Daniel; D. Lopes, João; Duarte, Rui Policarpo; Véstias, Mário; Neto, Horácio C; De Sousa, Jose. "Configurable hardware core for IoT object detection". (2021): http://hdl.handle.net/10400.21/13952.
    Published • 10.3390/fi13110280
  14. Pestana, Daniel; Miranda, Pedro R.; Lopes, João D.; Duarte, Rui; Véstias, Mário; Neto, Horácio C; De Sousa, Jose. "A full featured configurable accelerator for object detection with YOLO". (2021): http://hdl.handle.net/10400.21/13689.
    Published • 10.1109/ACCESS.2021.3081818
  15. Mário Véstias. "Efficient Design of Pruned Convolutional Neural Networks on FPGA". Journal of Signal Processing Systems (2020): https://doi.org/10.1007/s11265-020-01606-2.
    Published • 10.1007/s11265-020-01606-2
  16. Véstias, Mário P.; Duarte, Rui P.; de Sousa, José T.; Neto, Horácio C.. "A fast and scalable architecture to run convolutional neural networks in low density FPGAs". Microprocessors and Microsystems 77 (2020): 103136. http://dx.doi.org/10.1016/j.micpro.2020.103136.
    Published • 10.1016/j.micpro.2020.103136
  17. Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto. "Moving Deep Learning to the Edge". Algorithms 13 5 (2020): 125-125. https://doi.org/10.3390/a13050125.
    Published • 10.3390/a13050125
  18. Mario P. Vestias; Rui P. Duarte; Jose T. De Sousa; Horacio C. Neto. "A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs". IEEE Access 8 (2020): 107229-107243. https://doi.org/10.1109/ACCESS.2020.3000444.
    Published • 10.1109/ACCESS.2020.3000444
  19. Nascimento, Jose M. P.; Vestias, Mario P.; Martin, Gabriel. "Hyperspectral Compressive Sensing With a System-On-Chip FPGA". IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing 13 (2020): 3701-3710. http://dx.doi.org/10.1109/jstars.2020.2996679.
    Published • 10.1109/jstars.2020.2996679
  20. Vestias, Mario P.; Duarte, Rui P.; de Sousa, Jose T.; Neto, Horacio C.. "A fast and scalable architecture to run convolutional neural networks in low density FPGAs". Microprocessors and Microsystems (2020): https://publons.com/wos-op/publon/33055617/.
    Published • 10.1016/J.MICPRO.2020.103136
  21. Véstias, Mário P.; Duarte, Rui Policarpo; de Sousa, José T.; Neto, Horácio C.. "Fast Convolutional Neural Networks in Low Density FPGAs Using Zero-Skipping and Weight Pruning". Electronics 8 11 (2019): 1321. http://dx.doi.org/10.3390/electronics8111321.
    Published • 10.3390/electronics8111321
  22. Véstias, Mário P.. "A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing". Algorithms 12 8 (2019): 154. http://dx.doi.org/10.3390/a12080154.
    Published • 10.3390/a12080154
  23. VÉSTIAS, MÁRIO; Horácio C. Neto. "Improving the Area of Fast Parallel Decimal Multipliers". Journal of Microprocessors and Microsystems (2018):
    Published
  24. Duarte, Rui Policarpo; Véstias, Mário; Carvalho, Carlos; Casaleiro, João. "Stochastic theater: stochastic datapath generation framework for fault-tolerant IoT sensors". i-ETC: ISEL Academic Journal of Electronics, Telecommunications and Computers 4 1 (2018): http://hdl.handle.net/10400.21/9244.
    Published
  25. Vestias, Mario; Duarte, Rui Policarpo; de Sousa, Jose T.; Neto, Horacio. "Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs". 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL) (2018): https://publons.com/wos-op/publon/14574596/.
    10.1109/FPL.2018.00075
  26. VÉSTIAS, MÁRIO; Horácio C. Neto. "Decimal Addition on FPGA based on a Mixed BCD/Excess-6 Representation". Journal of Microprocessors and Microsystems (2017):
    Published
  27. VÉSTIAS, MÁRIO; José Nascimento. "System-on-chip field-programmable gate array design for onboard real-time hyperspectral unmixing". Journal of Applied Remote Sensing 10 1 (2016):
    Published
  28. Canilho, Jose; Vestias, Mario; Neto, Horacio. "Multi-Core for K-Means Clustering on FPGA". 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL) (2016): https://publons.com/wos-op/publon/8658589/.
    10.1109/FPL.2016.7577313
  29. Nascimento, Jose M. P.; Vestias, Mario. "System-on-chip field-programmable gate array design for onboard real-time hyperspectral unmixing". Journal of Applied Remote Sensing (2016): https://publons.com/wos-op/publon/8642020/.
    10.1117/1.JRS.10.015004
  30. VÉSTIAS, MÁRIO; Wilson José; Ana Silva; Horácio C. Neto. "Algorithm-Oriented Design of Efficient Many-Core Architectures applied to Dense Matrix Multiplication". Analog Integrated Circuits and Signal Processing 42 1 (2015):
    Published
  31. José, Wilson M.; Silva, Ana Rita; Véstias, Mário; Neto, Horácio. "Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication". (2015): http://hdl.handle.net/10400.21/5739.
    10.1007/s10470-014-0441-7
  32. Duarte, Rui Policarpo; Vestias, Mario; Neto, Horacio. "Enhancing Stochastic Computations via Process Variation". 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL) (2015): https://publons.com/wos-op/publon/8658594/.
    10.1109/FPL.2015.7293962
  33. VÉSTIAS, MÁRIO; Ana Silva; Wilson José; Horácio C. Neto. "Using SystemC to Simulate a Many-Core Architecture". Procedia Technology (2014):
    Published
  34. Silva, Ana Rita; Jose, Wilson; Neto, Horacio; Vestias, Mario. "Modeling and Simulation of a Many-Core Architecture Using SystemC". Procedia Technology (2014): https://publons.com/wos-op/publon/54986315/.
    10.1016/J.PROTCY.2014.10.222
  35. Palhinha, Filipe; Pereira, Ricardo; Carona, Duarte; Serrador, Antonio; Vestias, Mario; Silva, Joao; Peres, Tiago; Silva, Pedro. "RF FRONT END RECEIVER FOR GPS/GALILEO L1/E1". Procedia Technology (2014): https://publons.com/wos-op/publon/31850102/.
    10.1016/J.PROTCY.2014.10.186
  36. Peres, T. R.; Silva, J. S.; Silva, P. F.; Carona, D.; Serrador, A.; Palhinha, F.; Pereira, R.; Vestias, M.. "MULTI-GNSS RECEIVER FOR AEROSPACE NAVIGATION AND POSITIONING APPLICATIONS". XXIII ISPRS Congress, Commission I (2014): https://publons.com/wos-op/publon/54986312/.
    10.5194/ISPRSARCHIVES-XL-3-W1-87-2014
  37. Silva, Jorge; Pinho, Pedro; Véstias, Mário. "DESIGN OF THE ALAMOUTI SCHEME FOR A MIMO RECEIVER AND ITS IMPLEMENTATION ON AN FPGA". (2013): http://journals.isel.pt/index.php/i-ETC/article/view/8.
  38. Jose, Wilson; Silva, Ana Rita; Neto, Horacio; Vestias, Mario. "ANALYSIS OF MATRIX MULTIPLICATION ON HIGH DENSITY VIRTEX-7 FPGA". 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL) (2013): https://publons.com/wos-op/publon/8658600/.
    10.1109/FPL.2013.6645604
  39. Silva, Victor; Fernandes, Jorge; Vestias, Mario; Neto, Horacio. "A RECONFIGURABLE COMPUTING ARCHITECTURE USING MAGNETIC TUNNELING JUNCTION MEMORIES". 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL) (2013): https://publons.com/wos-op/publon/8658601/.
    10.1109/FPL.2013.6645616
  40. Pinho, P.; Vestias, M.. "A High-Rate MIMO Receiver in an FPGA". IEEE Antennas and Propagation Society, AP-S International Symposium (Digest) (2012): http://www.scopus.com/inward/record.url?eid=2-s2.0-84870555407&partnerID=MN8TOARS.
    10.1109/APS.2012.6348078
  41. Vestias, Mario; Sarmento, Helena. "FPGA Implementation of IEEE 802.15.3c Receiver". IEEE TENTH INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS, PROCEEDINGS (2012): https://publons.com/wos-op/publon/54986314/.
  42. Silva, V.; Duarte, R.; Véstias, M.; Neto, H.. "Multiplier-based double precision floating point divider according to the IEEE-754 standard". Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 4943 LNCS (2008): 262-267. http://www.scopus.com/inward/record.url?eid=2-s2.0-51849166463&partnerID=MN8TOARS.
    10.1007/978-3-540-78610-8_26
  43. Véstias, M.P.; Neto, H.C.. "Area/performance improvement of NoC architectures". Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 3985 LNCS (2006): 193-198. http://www.scopus.com/inward/record.url?eid=2-s2.0-33748989517&partnerID=MN8TOARS.
Magazine article
  1. VÉSTIAS, MÁRIO; João Cardoso. "Architectures and Compilers to Support Reconfigurable Computing", ACM Crossroads, 1999
Thesis / Dissertation
  1. Mota, David José Queirós Mesquita Mourato. "LITESAR – Sistema de análise de imagens SAR em tempo-real". Master, 2021. http://hdl.handle.net/10400.21/14326.
  2. Khanpour, Hamid. "MPLS layer 3 VPN". Master, 2018. http://hdl.handle.net/10400.21/8848.
  3. Almeida, Jaime Francisco Saraiva de. "Algoritmos de estimação da direção de chegada de sinal". Master, 2015. http://hdl.handle.net/10400.21/6007.
  4. Rodrigues, Tiago Augusto Nunes. "JPEG decoder implementation on FPGA using dynamic partial reconfiguration". Master, 2015. http://hdl.handle.net/10400.21/5375.
  5. Rosário, João Pedro José do. "Implementação em hardware reconfigurável de método de separação de dados hiperespetrais". Master, 2014. http://hdl.handle.net/10400.21/4194.
  6. Mália, Wilson Alexandre Borges. "Many-core approach to 2D-DCT calculation using an FPGA". Master, 2014. http://hdl.handle.net/10400.21/4345.
  7. Pereira, Ricardo Joel Martins. "Sistema de multiprocessamento para simulação de N-corpos em FPGA". Master, 2013. http://hdl.handle.net/10400.21/3366.
  8. Ponte, Pedro Guilherme Amaral da. "Projecto de uma câmara em rede em FPGA". Master, 2013. http://hdl.handle.net/10400.21/3297.
  9. Silva, Jorge Tiago Pereira Mogas da. "Receptor MIMO em FPGA baseado no esquema de Alamouti". Master, 2011. http://hdl.handle.net/10400.21/1195.

Other

Other output
  1. Actas das VII Jornadas sobre Sistemas Reconfiguráveis. 2011. Mário Véstias; João Canas Ferreira. http://repositorio.inesctec.pt/handle/123456789/3226.
Activities

Supervision

Thesis Title
Role 		Degree Subject (Type)
Institution / Organization
2022/01/05 - Current Compiling Algorithms to Coarse-Grain Reconfigurable Architectures
Co-supervisor
 Ciências de Engenharia (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2010/09/29 - Current Analisador Espectral em FPGA
Supervisor
 Engenharia de Sistemas das Telecomunicações e Electrónica (Degree)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2022 - 2023 Hyperspectral Image Classification on FPGA with Convolutional Neural Network
Co-supervisor
Universidade de Lisboa Instituto Superior Técnico, Portugal
2022 - 2023 Urban Object Detection using Convolutional Neural Networks on FPGAs
Co-supervisor
Universidade de Lisboa Instituto Superior Técnico, Portugal
2022 - 2023 Lidar-based 3D Object Detection in FPGA
Co-supervisor
Universidade de Lisboa Instituto Superior Técnico, Portugal
2021 - 2022 Hardware Acceleration of CNN-Based Image Segmentation for Fire Detection
Co-supervisor
Universidade de Lisboa Instituto Superior Técnico, Portugal
2021 - 2022 Intelligent traffic control system for connected vehicles using VLC
Supervisor
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2021 - 2022 Intelligent Health Device based on Deep Learning
Supervisor
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2020/09/28 - 2021/07/14 SoC-FPGA MobileNets for Embedded Vision Applications
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020/09/06 - 2021/07/10 SoC-FPGA Binary Convolutional Neural Networks
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2021 - 2021 Software/hardware architectures for implementing Natural Language Processing (NLP) applications
Supervisor
 Engenharia Electrotécnica e de Computadores (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2021 - 2021 LITESAR - Sistema de Análise de Imagens SAR em Tempo-Real
Supervisor
 Engenharia de Electrónica e Telecomunicações (Master)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2019 - 2019 Otimização de Redes Neuronais Convolucionais em FPGA com Redução do Tamanho dos Operandos
Supervisor
 Engenharia de Electrónica e Telecomunicações (Master)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2019 - 2019 Otimização de Redes Neuronais Convolucionais em FPGA utilizando Técnicas de Compressão
Supervisor
 Engenharia de Electrónica e Telecomunicações (Master)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2017/09/30 - 2018/07/20 Implementação de filtros de imagem em FPGA usando ferramentas de síntese de alto nível
Supervisor
 Engenharia Electrónica e de Telecomunicações (Master)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2017/09/30 - 2018/07/08 Monitoring system for Fitness Health
Supervisor
 Engenharia de Eletrónica e Telecomunicações (Master)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2018 - 2018 MPLS Layer 3 VPN Hamid Khanpour
Supervisor
 Engenharia de Electrónica e Telecomunicações (Master)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2015 - 2015 Avaliação do desempenho de uma tracking antena em GSM-R
Supervisor
 Engenharia de Electrónica e Telecomunicações (Master)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2015 - 2015 JPEG Decoder implementation on FPGA using Dynamic Partial Reconfiguration
Supervisor
 Engenharia de Electrónica e Telecomunicações (Master)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2014 - 2014 Many-Core Approach to 2D-DCT Calculation
Supervisor
 Engenharia de Electrónica e Telecomunicações (Master)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2014 - 2014 Implementação em hardware reconfigurável de método de separação de dados hiperespetrais
Supervisor
 Engenharia de Electrónica e Telecomunicações (Master)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2013 - 2013 Sistema de Multiprocessamento para Simulação de N-corpos em FPGA
Supervisor
 Engenharia de Electrónica e Telecomunicações (Master)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2013 - 2013 Projeto de uma Câmara em Rede em FPGA
Supervisor
 Engenharia de Electrónica e Telecomunicações (Master)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2010/09/30 - 2011/10/30 Projecto de um Receptor MIMO baseado em FPGA
Supervisor
 Engenharia de Sistemas das Telecomunicações e Electrónica (Master)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2010/09/29 - 2011/10/30 Analisador de Tráfego Ethernet em FPGA
Supervisor
 Engenharia de Sistemas das Telecomunicações e Electrónica (Degree)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2011 - 2011 Using reconfigurable computing to improve the performance of massively parallel processing architectures
Supervisor
 Engenharia Electrotécnica e de Computadores (PhD)
Universidade NOVA de Lisboa Faculdade de Ciências e Tecnologia, Portugal
2009/09/29 - 2010/07/30 Monitorização da central das ondas do Pico
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2009/09/29 - 2010/07/27 Visualizador de Consumo de Energia com Comunicação PLC / ZigBee
Supervisor
 Engenharia de Sistemas das Telecomunicações e Electrónica (Degree)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2008/09/30 - 2009/10/30 Interruptor programável sem Fios
Supervisor
 Engenharia de Eletrónica e Telecomunicações (Degree)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2008/09/30 - 2009/09/30 Projecto de um Divisor Decimal em FPGA
Supervisor
 Engenharia de Eletrónica e Telecomunicações (Master)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2008/09/30 - 2009/07/30 Medidor de Custos de Energia sem Fios
Supervisor
 Engenharia de Sistemas das Telecomunicações e Electrónica (Degree)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2008/09/30 - 2009/07/30 Receptor DVB-T com interface HDMI
Supervisor
 Engenharia de Sistemas das Telecomunicações e Electrónica (Degree)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2008/09/28 - 2009/07/19 Sistema Reconfigurável para Processamento de Imagens
Supervisor
 Engenharia de Eletrónica e Telecomunicações (Degree)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2008/09/20 - 2009/07/15 Emulador de um Modelo do Canal de Sistemas UWB
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2007/09/15 - 2008/06/15 Reconfigurable Hardware for Scientific Computing
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2006/09/15 - 2007/09/15 Câmara em Rede com Tecnologia FPGA
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2004/09/15 - 2005/07/20 Projecto e implementação do processo de encaminhamento de um router em FPGA
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Degree)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2004/09/15 - 2005/07/15 Aceleração de VOIP com hardware reconfigurável
Co-supervisor
 Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Degree)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2003 - 2004/09/22 Ferramentas eRH de apoio à Gestão de Recursos Humanos
Supervisor
 Engenharia e Tecnologias Informáticas (Degree)
Universidade Autónoma de Lisboa, Portugal
2003/09/22 - 2004/07/04 Acesso Web a uma base de dados de uma biblioteca
Supervisor
 Engenharia e Tecnologias Informáticas (Degree)
Universidade Autónoma de Lisboa, Portugal