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February 2021 Dr. Diniz received his BSc. and M.Sc. in Electrical and Computer Engineering from the Technical University in Lisbon, Portugal and in 1997 his Ph.D. in Computer Science from the University of California, Santa Barbara, USA. From 1997 to 2017 he was a Research Associate with the University of Southern California¿s Information Sciences Institute (USC/ISI) and a Research Assistant Professor of Computer Science at the University of Southern California (USC) in Los Angeles, California. In 2000 he co-founded and was the V.P. for Engineering of Quantum Semiconductor (QSemi), a semiconductor company in San Jose, California, and from 2017 to 2019 he was a Senior Scientist at Custom Silicon Solutions (CSS), a small company specializing in advanced VLSI full-custom and high-performance IC solutions. He was a Senior Researcher with INESC-ID in Lisbon and recently joined the Informatics Engineering Department at the Faculdade de Engenharia da Universidade do Porto as a Full Professor where he is engaged in various research aspects related to high-performance and efficient computing as well as large-scale simulations for the application domain of urban mobility and autonomous vehicles. At USC/ISI he led a small research group focusing on the application of compilation and synthesis techniques for high-performance embedded and reconfigurable computing. Over the years, and while at USC/ISI, he funded his own salary (100%) and those of his graduate students, through a long series of research grants from the US National Science Foundation (NSF), US Department of Defense (DoE) and US Department of Energy (DoE) with an estimated annual budget of $500K for him and his research group. From 2007 to 2009 he took a sabbatical from USC/ISI and joined the Technical University of Lisbon (IST) in Lisbon, Portugal as an Associate Professor with the Informatics Engineering Department where, in addition to his teaching duties, he was the co-PI of an EC-funded FP7 Programme project among other nationally-funded research projects. Throughout his professional career, he has been the technical and management lead of a long list of research contracts and grants, being responsible for a wide range of reporting and publication activities as well as presenting findings at scholarly events. He graduated 5 PhD students both at USC and at IST and has authored or co-authored 28 internationally recognized scientific journal articles and over 75 international conference papers (all peer reviewed). He is also the author or co-author of 3 scientific textbooks and editor of more than 10 international conference and symposia proceedings or scientific journal special issues. His industrial involvement at CSS led to the development of various commercial deployed products for the embedded electronics market while at QSemi he was responsible for the design and implementation of several circuit-level designs resulting in 5 patens, all granted in the US, and pending elsewhere. Over the years, he has been heavily involved in the scientific community having participated as part of the technical program committee of over 25 international conferences and workshops in the scientific area of high-performance computing and reconfigurable computing being invited as keynote speaker and guest lecturer at various of these events. He is regularly a reviewer for scientific journals in his areas of research and has participated as a panelist in a large number of international scientific review meetings both in the US and in Europe. As faculty in the US and in Portugal he was responsible and teaching many semester-level courses in Computer Science and Engineering, as well as various short courses and seminars in Germany and Brazil. He was born in Lisbon, Portugal, in 1965 and has exclusively held the Portuguese citizenship.
Read full resume ↓
Identification

Personal identification

Full name
Pedro Nuno Ferreira da Rosa da Cruz Diniz

Citation names

  • DINIZ, PEDRO
  • DINIZ, PEDRO C.

Author identifiers

Ciência ID
3D16-9F6F-D262
ORCID iD
0000-0003-3131-9367

Email addresses

  • pedrodiniz@fe.up.pt (Professional)

Websites

Languages

Language Speaking Reading Writing Listening Peer-review
English Advanced (C1) Advanced (C1) Advanced (C1) Advanced (C1)
Portuguese Advanced (C1) Advanced (C1) Advanced (C1) Advanced (C1)
Education
Degree Classification
2017/11/01
Concluded
 Engenharia Informática (Título de Agregado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"n/a" (THESIS/DISSERTATION)
 Aprovado
1992/09/01 - 1997/08/01
Concluded
 Computer Science (Doktor (PhD))
Major in Computer Science
University of California Santa Barbara Department of Computer Science, United States
"Commutativity Analysis : A New Analysis Framework for Parallelizing Compilers" (THESIS/DISSERTATION)
 Muito Bom
1991/08/01
Concluded
 Computer Engineering (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Arquitectura de um Multiprocessor Orientado para Objectos" (THESIS/DISSERTATION)
 Muito Bom
1988/08/01
Concluded
 Computer Engineering (Licenciatura)
Universidade de Lisboa Instituto Superior Técnico, Portugal
 18 valores
Affiliation

Science

Category
Host institution 		Employer
1997/08/01 - 2017/06/30 Researcher (Research) University of Southern California, United States
Information Sciences Institute, United States

Teaching in Higher Education

Category
Host institution 		Employer
2022/02/28 - Current Full Professor (University Teacher) Universidade do Porto, Portugal
Universidade do Porto Faculdade de Engenharia, Portugal
1998/08/01 - 2017/06/30 Invited Assistant Professor (University Teacher) University of Southern California, United States
Information Sciences Institute, United States
2006/07/01 - 2008/06/30 Associate Professor (University Teacher) Instituto Superior Técnico, Departamento de Engenharia Informática, Portugal

Positions / Appointments

Category
Host institution 		Employer
2019/10/01 - 2022/02/27 Research Associate Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2000/04/21 - 2019/08/31 Vice-President Quantum Semiconductor, LLC, United States
Quantum Semiconductor, LLC, United States
2017/08/01 - 2019/07/31 Senior Scientist Custom Silicon Solutions (CSS), United States
Custom Silicon Solutions (CSS), United States
Projects

Grant

Designation Funders
2013/04/01 - 2016/03/31 Collaborative Research: Localized, Layered Formal Hardware/Software Resilience Methods
info:eu-repo/grantAgreement/NSF/Directorate for Computer & Information Science & Engineering/1255776/US
Principal investigator
University of Southern California, United States
 National Science Foundation
Concluded
2013/01/01 - 2014/12/31 FAIL-SAFE: Fault Aware IntelLigent SoftwAre For Exascale
63295-CA-ACI.9
Principal investigator
University of Southern California, United States
 US Army Research Laboratory
Concluded
2011/12/31 - 2014/09/01 Energy-Efficient Memory-Oriented Exascale-Enable Microarchitectures
SNL-ACS-0040
Principal investigator
University of Southern California, United States
 Sandia National Laboratories
Concluded
2007/12/01 - 2010/12/31 AMADEUS: ASPECTS AND COMPILER OPTIMIZATIONS FOR MATLAB SYSTEM DEVELOPMENT
info:eu-repo/grantAgreement/FCT/5876-PPCDTI/70271/PT
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Universidade do Algarve Faculdade de Ciências e Tecnologia
2006/08/01 - 2009/07/31 VECTOR: Matlab Complation and Hardware Synthesis of Custom-Vector Processing for Image and Signal Processing Algorithms.
PTDC/EEA-ELC/71556/2006
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2005/12/01 - 2008/11/30 DDDAS-SMRP: Optimizing Signal and Image Processing in a Dynamic, Data-Driven Application System.
0911750
Principal investigator
University of Southern California, United States
 National Science Foundation
Concluded
2002/08/01 - 2006/07/31 SLATE: Compiler-driven Design Space Exploration for Heterogeneous System-on-a-Chip
CCR-0209228
Principal investigator
National Science Foundation
Concluded
2002/11/30 - 2005/09/30 COMPILE: Resource-Aware Off-line and On-line Empirical Optimization
0204040
Principal investigator
University of Southern California, United States
Concluded
2002/01/01 - 2004/12/31 REFLECT: Rendering FPGAs to Multi-Core Embedded Computing
248976
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 European Commission
Concluded
1998/06/01 - 2002/05/31 DEFACTO: A Design Environment for Reconfigurable Computing Technology
DARPA-ACS-00040
Supervisor
University of Southern California, United States
Concluded

Contract

Designation Funders
2011/09/01 - 2016/08/31 SUPER: The Institute for Sustained Performance, Resilience, and Energy
DE-SC0006733
Researcher
University of Southern California, United States
 US Department of Energy Germantown
Concluded
2004/08/08 - 2007/07/31 PetaScale Execution Time Evaluation
00000000
Researcher
University of Southern California, United States
 US Department of Energy Germantown
Concluded
Outputs

Publications

Book
  1. Hochberger, C.; Nelson, B.; Koch, A.; Woods, R.; Diniz, P.. Preface. 2019.
  2. Cardoso, J. M.P.; Coutinho, Jose G.F.; DINIZ, PEDRO. Embedded Computing for High Performance : Efficient Mapping of Computations Using Customization, Code Transformations and Compilation. Elsevier. 2017.
    Published
  3. Faculdade de Engenharia. REFLECT: rendering FPGAs to multi-core embedded computing. 2011.
  4. João M.P. Cardoso; Pedro C. Diniz. Compilation Techniques for Reconfigurable Architectures. 2009.
    10.1007/978-0-387-09671-1
  5. Cardoso, J.M.P.; DINIZ, PEDRO. Compilation Techniques for Reconfigurable Architectures. Springer. 2008.
    Published
Conference paper
  1. Bartolini, A.; Cardoso, J.M.P.; Silvano, C.; Palermo, G.; Barbosa, J.; Marongiu, A.; Mustafa, D.; et al. "Message from ANDARE'17 general and program chairs". 2017.
  2. Silva, Bruno; Delbem, Alexandre; Bonato, Vanderlei; DINIZ, PEDRO. "Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systems". Cancun, 2015.
    Published • 10.1109/reconfig.2015.7393355
  3. DINIZ, PEDRO C.. "Atomic-delayed execution: A concurrent programming model for incomplete graph-based computations". 2015.
    Published • 10.1109/hpec.2015.7322468
  4. Park, Joonseok; DINIZ, PEDRO. "Evaluating High-Level Program Invariants Using Reconfigurable Hardware". Paper presented in Applied Reconfigurable Computing Symposium, Vilamoura, 2014.
    Published
  5. Bispo, Joao; Pinto, Pedro; Nobre, Ricardo; Carvalho, Tiago; Cardoso, Joao M. P.; Diniz, Pedro C.. "The MATISSE MATLAB compiler". Paper presented in EEE International Conference on Industrial Informatics (INDIN), 2012.
    Published • 10.1109/indin.2013.6622952
  6. Cardoso, João M.P.; Teixeira, João; Alves, Jose C.; Nobre, Ricardo; Diniz, Pedro C.; Coutinho, Jose G.F.; Luk, Wayne. "Specifying Compiler Strategies for FPGA-based Systems". 2012.
    Published • 10.1109/fccm.2012.41
  7. Cardoso, João M.P.; Carvalho, Tiago; Coutinho, José G.F.; Luk, Wayne; Nobre, Ricardo; Diniz, Pedro; Petrov, Zlatko. "LARA". Potsdam, 2012.
    10.1145/2162049.2162071
  8. Gohringer, D.; Diniz, P.. "Special session on 'programming paradigms for reconfigurable multi-core embedded systems'". 2012.
    10.1109/SAMOS.2012.6404178
  9. Becker, J.; Benoit, P.; Cumplido, R.; Prasanna, V.K.; Vaidyanathan, R.; Hartenstein, R.; Areibi, S.; et al. "Introduction". 2011.
    10.1109/IPDPS.2011.396
  10. Monteiro, Miguel Pessoa; Saraiva, João Alexandre; Fernandes, João M.; Cardoso, João M. P.; Diniz, Pedro C.. "A domain-specific aspect language for transforming MATLAB programs". 2010.
  11. Augusto, C.J.R.P.; Forester, L.; Diniz, P.. "On the possibility of SiGeC superlattices having a broken-gap". 2010.
    10.1109/GROUP4.2010.5643351
  12. Augusto, C.J.R.P.; Forester, L.; Diniz, P.. "SiGeC avalanche light emitters integrated with CMOS". 2010.
    10.1109/GROUP4.2010.5643350
  13. Augusto, C.; Forester, L.; Diniz, P.C.. "A new CMOS SiGeC avalanche photo-diode pixel for IR sensing". 2009.
    10.1117/12.818269
  14. Rodrigues, Rui; Cardoso, Joao M.P.; Diniz, Pedro C.. "A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops". Paper presented in 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, 2007.
    Published • 10.1109/fccm.2007.16
Edited book
  1. DINIZ, PEDRO. Applied Reconfigurable Computing. Architectures, Tools, and Applications. Springer International Publishing. 2020.
    Published • 10.1007/978-3-030-44534-8 • Editor
  2. DINIZ, PEDRO. Applied Reconfigurable Computing. Springer International Publishing. 2019.
    Published • 10.1007/978-3-030-17227-5 • Editor
  3. DINIZ, PEDRO. Applied Reconfigurable Computing. Architectures, Tools, and Applications. Springer International Publishing. 2018.
    Published • 10.1007/978-3-319-78890-6 • Editor
  4. DINIZ, PEDRO. Applied Reconfigurable Computing. Springer International Publishing. 2015.
    Published • 10.1007/978-3-319-16214-0 • Editor
Journal article
  1. Alberto Oliveira de Souza Junior, Carlos; Bispo, João; Cardoso, João M. P.; DINIZ, PEDRO; Marques, Eduardo. "Exploration of FPGA-Based Hardware Designs for QR Decomposition for Solving Stiff ODE Numerical Methods Using the HARP Hybrid Architecture". Electronics 9 5 (2020): 843. http://dx.doi.org/10.3390/electronics9050843.
    Published • 10.3390/electronics9050843
  2. de Souza Rosa, L.; Dasu, A.; C. Diniz, P.; Bonato, V.; de Souza Rosa, Leandro; Dasu, Aravind; DINIZ, PEDRO (3D16-9F6F-D262); Bonato, Vanderlei. "A Faddeev Systolic Array for EKF-SLAM and its Arithmetic Data Representation Impact on FPGA". Journal of Signal Processing Systems 90 3 (2018): 357-369. http://www.scopus.com/inward/record.url?eid=2-s2.0-85017465179&partnerID=MN8TOARS.
    Published • 10.1007/s11265-017-1243-9
  3. Hukerikar, Saurabh; Teranishi, Keita; Diniz, Pedro C.; Lucas, Robert F.. "RedThreads: An Interface for Application-Level Fault Detection/Correction Through Adaptive Redundant Multithreading". International Journal of Parallel Programming 46 2 (2017): 225-251. http://dx.doi.org/10.1007/s10766-017-0492-3.
    Published • 10.1007/s10766-017-0492-3
  4. Park, Joonseok; DINIZ, PEDRO (3D16-9F6F-D262). "Program-Invariant Checking for Soft-Error Detection using Reconfigurable Hardware". ACM Transactions on Reconfigurable Technology and Systems 9 1 (2015): 1-13. http://dx.doi.org/10.1145/2751563.
    Published • 10.1145/2751563
  5. Silva, Bruno de Abreu; Delbem, Alexandre C.B.; Cuminato, Lucas A.; Bonato, Vanderlei; DINIZ, PEDRO C.. "Application-oriented cache memory configuration for energy efficiency in multi-cores". IET Computers & Digital Techniques 9 1 (2015): 73-81. http://dx.doi.org/10.1049/iet-cdt.2014.0091.
    Published • 10.1049/iet-cdt.2014.0091
  6. Cardoso, João M. P.; Coutinho, José G. F.; Carvalho, Tiago; Diniz, Pedro C.; Petrov, Zlatko; Luk, Wayne; Gonçalves, Fernando. "Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach". Software: Practice and Experience 46 2 (2014): 251-287. http://dx.doi.org/10.1002/spe.2301.
    Published • 10.1002/spe.2301
  7. Santos, Andre C.; Cardoso, Joao M. P.; Diniz, Pedro C.; Ferreira, Diogo R.; Petrov, Zlatko. "Specifying Dynamic Adaptations for Embedded Applications Using a DSL". IEEE Embedded Systems Letters 6 3 (2014): 49-52. http://dx.doi.org/10.1109/les.2014.2321325.
    Published • 10.1109/les.2014.2321325
  8. Santos, André C.; Cardoso, João M. P.; Diniz, Pedro C.; Ferreira, Diogo R.; Petrov, Zlatko. "A DSL for specifying run-time adaptations for embedded systems: an application to vehicle stereo navigation". The Journal of Supercomputing 70 3 (2014): 1218-1248. http://dx.doi.org/10.1007/s11227-014-1192-z.
    Published • 10.1007/s11227-014-1192-z
  9. Snir, Marc; Wisniewski, Robert W; Abraham, Jacob A; Adve, Sarita V; Bagchi, Saurabh; Balaji, Pavan; Belak, Jim; et al. "Addressing failures in exascale computing". The International Journal of High Performance Computing Applications 28 2 (2014): 129-173. http://dx.doi.org/10.1177/1094342014522573.
    Published • 10.1177/1094342014522573
  10. Cardoso, João M.P.; Carvalho, Tiago; Coutinho, José G.F.; Nobre, Ricardo; Nane, Razvan; Diniz, Pedro C.; Petrov, Zlatko; Luk, Wayne; Bertels, Koen. "Controlling a complete hardware synthesis toolchain with LARA aspects". Microprocessors and Microsystems 37 8 (2013): 1073-1089. http://dx.doi.org/10.1016/j.micpro.2013.06.001.
    Published • 10.1016/j.micpro.2013.06.001
  11. Park, Joonseok; DINIZ, PEDRO C.. "Data Reorganization and Prefetching of Pointer-Based Data Structures". IEEE Design & Test of Computers 28 4 (2011): 38-47. http://dx.doi.org/10.1109/mdt.2011.45.
    Published • 10.1109/mdt.2011.45
  12. Demertzi, Melina; DINIZ, PEDRO; Hall, Mary W.; Gilbert, Anna C.; Wang, Yi. "Domain-Specific Optimization of Signal Recognition Targeting FPGAs". ACM Transactions on Reconfigurable Technology and Systems 4 2 (2011): 1-26. http://dx.doi.org/10.1145/1968502.1968508.
    Published • 10.1145/1968502.1968508
  13. Cardoso, João M. P.; DINIZ, PEDRO; Weinhardt, Markus. "Compiling for reconfigurable computing". ACM Computing Surveys 42 4 (2010): 1-65. http://dx.doi.org/10.1145/1749603.1749604.
    Published • 10.1145/1749603.1749604
  14. Santos, André C.; Cardoso, João M.P.; Ferreira, Diogo R.; DINIZ, PEDRO; Chaínho, Paulo. "Providing user context for mobile and social networking applications". Pervasive and Mobile Computing 6 3 (2010): 324-341. http://dx.doi.org/10.1016/j.pmcj.2010.01.001.
    Published • 10.1016/j.pmcj.2010.01.001
  15. Figo, Davide; DINIZ, PEDRO; Ferreira, Diogo R.; Cardoso, João M. P.. "Preprocessing techniques for context recognition from accelerometer data". Personal and Ubiquitous Computing 14 7 (2010): 645-662. http://dx.doi.org/10.1007/s00779-010-0293-9.
    Published • 10.1007/s00779-010-0293-9
  16. Baradaran, Nastaran; DINIZ, PEDRO. "A compiler approach to managing storage and memory bandwidth in configurable architectures". ACM Transactions on Design Automation of Electronic Systems 13 4 (2008): 1-26. http://dx.doi.org/10.1145/1391962.1391969.
    Published • 10.1145/1391962.1391969
  17. Park, Joonseok; DINIZ, PEDRO. "Partial data reuse for nested loop computations: design space exploration for FPGA implementations". International Journal of Electronics 95 7 (2008): 705-723. http://dx.doi.org/10.1080/00207210801924396.
    Published • 10.1080/00207210801924396
  18. Chen, Chun; Chame, Jacqueline; Nelson, Yoonju Lee; DINIZ, PEDRO; Hall, Mary; Lucas, Robert. "Compiler-assisted performance tuning". Journal of Physics: Conference Series 78 (2007): 012024. http://dx.doi.org/10.1088/1742-6596/78/1/012024.
    Published • 10.1088/1742-6596/78/1/012024
  19. Baradaran, N.; DINIZ, PEDRO. "Exploiting parallelism in configurable architectures through custom array mapping". IET Computers & Digital Techniques 1 4 (2007): 303. http://dx.doi.org/10.1049/iet-cdt:20060181.
    Published • 10.1049/iet-cdt:20060181
  20. Lee, Yoon-Ju; DINIZ, PEDRO; Hall, Mary W.; Lucas, Robert. "Empirical Optimization for a Sparse Linear Solver: A Case Study". International Journal of Parallel Programming 33 2-3 (2005): 165-181. http://dx.doi.org/10.1007/s10766-005-3581-7.
    Published • 10.1007/s10766-005-3581-7
  21. DINIZ, PEDRO; Hall, Mary; Park, Joonseok; So, Byoungro; Ziegler, Heidi. "Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system". Microprocessors and Microsystems 29 2-3 (2005): 51-62. http://dx.doi.org/10.1016/j.micpro.2004.06.007.
    Published • 10.1016/j.micpro.2004.06.007
  22. Joonseok Park; DINIZ, PEDRO; Shesha Shayee, K.R.. "Performance and area modeling of complete FPGA designs in the presence of loop transformations". IEEE Transactions on Computers 53 11 (2004): 1420-1435. http://dx.doi.org/10.1109/tc.2004.101.
    Published • 10.1109/tc.2004.101
  23. Rinard, Martin C.; DINIZ, PEDRO. "Eliminating synchronization bottlenecks using adaptive replication". ACM Transactions on Programming Languages and Systems (TOPLAS) 25 3 (2003): 316-359. http://dx.doi.org/10.1145/641909.641911.
    Published • 10.1145/641909.641911
  24. DINIZ, PEDRO; Rinard, Martin C.. "Synchronization transformations for parallel computing". Concurrency: Practice and Experience 11 13 (1999): 773-802. http://dx.doi.org/10.1002/(sici)1096-9128(199911)11:13<773::aid-cpe453>3.0.co;2-5.
    Published • 10.1002/(sici)1096-9128(199911)11:13<773::aid-cpe453>3.0.co;2-5
  25. DINIZ, PEDRO; Rinard, Martin C.. "Eliminating synchronization overhead in automatically parallelized programs using dynamic feedback". ACM Transactions on Computer Systems 17 2 (1999): 89-132. http://dx.doi.org/10.1145/312203.312210.
    Published • 10.1145/312203.312210
  26. DINIZ, PEDRO; Rinard, Martin C.. "Lock Coarsening: Eliminating Lock Overhead in Automatically Parallelized Object-Based Programs". Journal of Parallel and Distributed Computing 49 2 (1998): 218-244. http://dx.doi.org/10.1006/jpdc.1998.1441.
    Published • 10.1006/jpdc.1998.1441
  27. Ibarra, Oscar H.; DINIZ, PEDRO; Rinard, Martin C.. "On the Complexity of Commutativity Analysis". International Journal of Foundations of Computer Science 08 01 (1997): 81-94. http://dx.doi.org/10.1142/s0129054197000069.
    Published • 10.1142/s0129054197000069
  28. Rinard, Martin C.; DINIZ, PEDRO. "Commutativity analysis". ACM SIGPLAN Notices 31 5 (1996): 54-67. http://dx.doi.org/10.1145/249069.231390.
    Published • 10.1145/249069.231390

Intellectual property

Patent
  1. Augusto, Carlos, J. R. P.; DINIZ, PEDRO. 2020. "Pixel for Use With Light Having Wide Intensity Range". United States.
    Granted/Issued
  2. Augusto, Carlos, J. R. P.; DINIZ, PEDRO. 2009. "Multi-mode ADC and its application to CMOS image sensors". United States.
    Granted/Issued
  3. Augusto, Carlos, J. R. P.; DINIZ, PEDRO. 2006. "Circuitry for Image Sensors with Avalanche Photodiodes". United States.
    Granted/Issued
  4. Augusto, Carlos, J. R. P.; DINIZ, PEDRO. 2006. "Asynchronous serial analog-to-digital converter methodology having dynamic adjustment of the bandwidth". United States.
    Granted/Issued
Activities

Oral presentation

Presentation title Event name
Host (Event location)
2019/03 The Promise of Reconfigurable Computing and its Challenges: Can FPGAs (really) Become Mainstream, and How?, Conference of Computational Interdisciplinary Science (CCIS 2019)
Georgia Tech School of Physics (Atlanta, United States)
2017/05/01 Managing Application Resilience: A Hybrid Programming Language and Run-Time Approach HPCAFE-2017: High-Performance Computing Approaches for Monitoring, Exploring, Optimizing and Autotuning workshop
Computing Systems Week (Bacelona, Spain)
2016/01/02 Managing Application Resilience: A Programming Language Approach PARMA-DITRAM workshop
HiPEAC (European Network of Excellence on High Performance and Embedded Architecture and Compilation) (Prague, Czech Republic)
2015/07/04 Managing Application Resilience: A Programming Language Approach
US National Institute of Standards and technology (NIST) (Germantown, United States)
2014/10/05 Managing Application Resilience: A Programming Language Approach High-Performance Computing Systems Symposium (WSCAD'14)
(São José dos Campos, Brazil)
2012/03/01 Tackling the Mapping and Tuning Problem for Embedded Multi-Core Systems W3 Friday Workshop "Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools and Applications"
(Dresden, Germany)
2011/05/03 The REFLECT Project – Using Aspects and Strategies for Design-Space-Exploration Reconfigurable Computing Cluster meeting as part of the technical program of the HiPEAC (European Network of Excellence on High Performance and Embedded Architecture and Compilation)
(Barcelona, Spain)

Supervision

Thesis Title
Role 		Degree Subject (Type)
Institution / Organization
2019/09/01 - Current Energy efficient scheduling techniques for high-performance heterogeneous computing architectures
Co-supervisor of Carlos Roberto Pereira Almeida Júnior
 Ciencia da Computação (PhD)
Universidade de São Paulo Câmpus de São Carlos, Brazil
2009/09/01 - 2013/07/01 A DSL-based Approach for the Specification of Software Adaptations in Embedded Systems
Co-supervisor of André G. N. Santos
 Engenharia Informática
Instituto Superior Técnico, Departamento de Engenharia Informática, Portugal
2003/08 - 2013/01/01 Resilience-Aware Scheduling
Supervisor of Jeremy Abramson
 Computer Science (PhD)
University of Southern California, United States
2004/08/01 - 2007/01/01 Compiler Directed Data Management for Configurable Architectures with Heterogeneous Memory Structures
Supervisor of Nastaran Baradaran
 Computer Science (PhD)
University of Southern California, United States
1999/09/01 - 2006/04/01 Automatic Application Mapping for Multi-FPGA Systems
Co-supervisor
 Computer Science (PhD)
University of Southern California, United States
2001/09/01 - 2004/08/01 Application-Specific External Memory Interfacing for FPGA-based Reconfigurable Architectures
Supervisor of Joonseok Park
 Computer Science (PhD)
University of Southern California, United States
1997/08/01 - 2002/02/01 A Methodology for Hardware/Software Co-design of Embedded Systems
Co-supervisor
 Computer Engineering (PhD)
University of Southern California, United States

Event organisation

Event name
Type of event (Role) 		Institution / Organization
2015/04/01 - 2015/04/03 General Co-Chair with M. Hübner, 11th Intl, Symp on Applied Reconfigurable Computing (ARC’15), Bochum, Germany, Apr., 2015 (2015/04/01 - 2015/04/03)
Symposium (Co-organisor)
2013/09/04 - 2013/09/06 Technical Program Co-Chair with K. Morrow, 23rd Intl. Symp. on Field Programmable Logic and Applications (FPL), Porto, Portugal, Sept., 2013. (2013/09/04 - 2013/09/06)
Conference (Member of the Scientific Committee)
2013/03/22 - 2013/03/24 General Chair of the 2013 Intl. Workshop on Applied Reconfigurable Computing (ARC’13), Los Angeles, CA, USA, Mar., 2013. (2013/03/22 - 2013/03/24)
Symposium (President of the Organising Committee)
 University of Southern California, United States

Consulting

Activity description Institution / Organization
2000/04/21 - 2019/08/31 Co-founder and VP of Engineering of this Start-Up Company focusing on Si-Ge-C based image sensors.
2013/07/01 - 2019/08/01 Responsible for the digital design of an high-performance computing ASIC for bit-coin computation implementing the SHA2 encryption arithmetic. This ASIC, designed full-custom and operational first silicon, was manufactured by Global Foundries, Germany, in 28 nm process technoogy is 23 mm by 25 mm big and includes 5.5 Billion transistors. Each chip, commercialized by Butterfly Labs constrains 1024 fully pipelined SHA2 engines reaching a 700Tera Hash/sec at 630 Watts and 300 Tera Hash/sec at 300 Watts. Custom Silicon Solutions (CSS), United States
2015/01/01 - 2018/01/01 Coordinates the Data Analytics effort at the Nano Engineering Applications start-up, in the collection and classification, using data-mining techniques, of the experimental laboratory data generated by carbon-nanotubes-based gas sensors to be manufactured and integrated in mobile devices.
Distinctions

Award

1988 Prémio Nacional para o Aluno de Engenharia mais bem classificado

Other distinction

1997 Fulbright Travel Grant