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José Monteiro received an Engineering and an MSc degrees in Electrical and Computer Engineering in 1989 and 1992 respectively, from the Technical University of Lisbon, and a PhD degree in Electrical Engineering and Computer Science in 1996 from the Massachusetts Institute of Technology. He is a Full Professor at Instituto Superior Técnico, and former Head of the Department of Computer Science and Engineering. He is a senior member of IEEE and a senior researcher at INESC-ID in Lisbon, having served as INESC-ID's director for 8 years. He has published over 120 research papers, and has been a member of numerous steering and technical program committees, having participated in the organization of several scientific events. He received Best Paper Awards from the IEEE Transactions on VLSI, and from two conferences. His main interests are in the areas of high-performance computing, computer architecture, parallel algorithms and design automation.
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Identification

Personal identification

Full name
José Carlos Alves Pereira Monteiro

Citation names

  • Monteiro, José

Author identifiers

Ciência ID
3A13-AD2C-6A3C
ORCID iD
0000-0003-0603-2268
Google Scholar ID
tkeh3OAAAAAJ

Email addresses

  • jcm@inesc-id.pt (Professional)

Knowledge fields

  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics

Languages

Language Speaking Reading Writing Listening Peer-review
English Advanced (C1) Advanced (C1) Advanced (C1) Advanced (C1)
French Intermediate (B1) Intermediate (B1) Beginner (A1) Intermediate (B1)
Spanish; Castilian Intermediate (B1) Advanced (C1) Beginner (A1) Intermediate (B1)
Portuguese Advanced (C1) Advanced (C1) Advanced (C1) Advanced (C1)
Education
Degree Classification
2012
Concluded
 Engenharia Informática e Computadores (Título de Agregado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Optimização de Circuitos para Processamento Digital de Sinais" (THESIS/DISSERTATION)
 Unanimidade
1996
Concluded
 Electrical Engineering and Computer Science (Doutoramento)
Massachusetts Institute of Technology, United States
"A Computer-Aided Design Methodology for Low Power Sequential Logic Circuits" (THESIS/DISSERTATION)
 Approved
1993
Concluded
 Mestrado em Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Codificação de Máquinas de Estados em Síntese Automática de Circuitos Lógicos" (THESIS/DISSERTATION)
 Muito Bom
1989
Concluded
 Licenciatura de Engenharia Electrotécnica e de Computadores (Licenciatura)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Simulação Lógica de Circuitos Digitais" (THESIS/DISSERTATION)
 17 / 20
Affiliation

Science

Category
Host institution 		Employer
1996/09/15 - Current Researcher (Research) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Teaching in Higher Education

Category
Host institution 		Employer
2016/12/22 - Current Full Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
2007/08/01 - 2016/12/22 Associate Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
1996/09/01 - 2007/05/31 Assistant Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
1995/02/01 - 1995/05/31 Assistant (University Teacher) Massachusetts Institute of Technology, United States
1990/09/01 - 1992/07/31 Trainee Assistant (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
1989/09/01 - 1990/07/31 Trainee Assistant (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal

Positions / Appointments

Category
Host institution 		Employer
2021/01/01 - Current Organic Unit Director INESC Lisboa, Portugal
2019/01/01 - 2020/12/31 Organic Unit President Universidade de Lisboa Instituto Superior Técnico, Portugal
IST, Computer Science and Engineering Department, Portugal
2008/01/01 - 2015/12/31 Organic Unit Director Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Others

Category
Host institution 		Employer
2017/01/01 - 2018/12/31 Vice-President of the Computer Science and Engineering Department in charge of graduation programs Universidade de Lisboa Instituto Superior Técnico, Portugal
2010/01/01 - 2018/12/31 Member of the Scientific Committee of the MSc in Information Systems and Computer Engineering. Universidade de Lisboa Instituto Superior Técnico, Portugal
2013/01/01 - 2014/12/31 Coordinator of the Masters Program in Computer Science and Engineering. Universidade de Lisboa Instituto Superior Técnico, Portugal
2009/09/01 - 2010/12/31 Coordinator of the Masters Program in Computer Science and Engineering. Universidade de Lisboa Instituto Superior Técnico, Portugal
2007/01/01 - 2008/12/31 Vice-President of the Computer Science and Engineering Department in charge of post-graduation programs Universidade de Lisboa Instituto Superior Técnico, Portugal
Projects

Grant

Designation Funders
2023/02/01 - 2026/01/31 URA-HPC, Ultra-Scalable Randomized Algorithms for Current and Future High Performance Supercomputers
2022.08838.PTDC
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Ongoing

Contract

Designation Funders
2018/10/01 - 2022/03/31 European joint Effort toward a Highly Productive Programming Environment for Heterogeneous Exascale Computing (EPEEC)
EPEEC
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 EU Framework Programme for Research and Innovation ICT Leadership in Enabling and Industrial Technologies
Concluded
2009/01/01 - 2015/12/31 Projecto Estratégico do INESC-ID
PEst-OE/EEI/LA0021
Other
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Ongoing
2012/03/01 - 2015/01/31 CerVANTES: Co-VAlidatioN Tool for Embedded Systems
PTDC/EEA-ELC/122756/2010
Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2013/04/01 - 2014/10 QCell - Configurable Logic Block Cell for Quaternary FPGAs
EXPL/EEI-ELC/1016/2012
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2012/06/01 - 2012/12/31 Time-multiplexed FIR Filters
Qualcomm
Qualcomm
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 QUALCOMM Inc
Concluded
2011/01/01 - 2012/06/30 Multicon - Architectural Optimization of DSP Systems with Multiple Constants Multiplications
PTDC/EEA-ELC/70025/2006
Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2007/11/01 - 2008/12/30 MABEL - Modeling Analog BEhavior using Learning techniques
POSI/EEA-ESE/61603/ESE/2004
Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2005/01/01 - 2008/06/30 PowerPlan - Electronic Systems Power Planning
POSC/EEAESE/61528/2004
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2001/01/01 - 2005/12 COOLCHIPS: An Environment for the Design and Analysis of Power Efficient Systems
POCTI 33705/ESE/1999
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
1999/11/01 - 2003/12/31 TGV: Técnicas para a Verificação da Funcionalidade Global de Sistemas Digitais Complexos
P/EEI/10204/98
Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
1997/02/01 - 2000/06/30 Técnicas de Projecto para Circuitos de Baixa Potência
PRAXIS 2/2.1/TIT/1563/95
Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
1997/11/01 - 1999/12/31 PCBIT: Low Power ISDN Interface for Portable Computers
ESPRIT 25.716
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 European Commission Seventh Framework Programme for Research and Technological Development IDEAS The European Research Council
Concluded
Outputs

Publications

Book
  1. Monteiro, José. VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things. Springer International Publishing. 2019.
    Published • 10.1007/978-3-030-15663-3 • Editor
  2. Arroz, Guilherme; Monteiro, José; Oliveira, Arlindo. Computer Architecture: Digital Circuits to Microprocessors. WORLD SCIENTIFIC. 2018.
    Published • 10.1142/10940
  3. Arroz, Guilherme; Monteiro, José; Oliveira, Arlindo. Arquitectura de Computadores: dos Sistemas Digitais aos Microprocessadores. IST Press. 2007.
    Published
  4. Monteiro, José; Devadas, Srinivas. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits. Springer US. 1997.
    Published • 10.1007/978-1-4615-6319-8
Book chapter
  1. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Multiplierless design of linear DSP transforms". In IFIP Advances in Information and Communication Technology, edited by Mir, Salvador; Tsui, Chi-Ying; Reis, Ricardo; Choy, Oliver, 73-93. Springer, 2012.
    Published • 10.1007/978-3-642-32770-4_5
  2. Gusmão, António; Silveira, L. Miguel; Monteiro, José. "Power Macro-Modeling Using an Iterative LS-SVM Method". In VLSI-SoC: Technologies for Systems Integration, edited by Becker, Jürgen; Johann, Marcelo; Reis, Ricardo, 118-134. Springer Berlin Heidelberg, 2011.
    Published • 10.1007/978-3-642-23120-9_7
  3. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Optimization Algorithms for Multiple Constant Multiplications". In Advanced Topics in VLSI Design, edited by Reis, Ricardo, 71-99. 2009.
    Published
  4. Rodrigues, Rui; Monteiro, José. "Review of the Algorithm Selection". In Computational Intelligence: Methods and Applications, edited by Rutkowski, Leszek. Exit Publishers, 2008.
    Published
  5. Oliveira, Leonardo; Santos, Cristiano; Ferrão, Daniel; Costa, Eduardo; Monteiro, José; Martins, João; Bampi, Sérgio; Reis, Ricardo. "A comparison of layout implementations of pipelined and non-pipelined signed radix-4 array multiplier and modified booth multiplier architectures". In VLSI-SoC: From Systems to Silicon, 25-39. IFIP International Federation for Information Processing, 2007.
    Published • 10.1007/978-0-387-73661-7_3
  6. Costa, Eduardo; Monteiro, José. "Gray encoded arithmetic operators applied to FFT and FIR dedicated datapaths". In VLSI-SOC: From Systems to Chips, 281-297. IFIP International Federation for Information Processing, 2006.
    Published
  7. Monteiro, José; Patel, Rakesh; Tiwari, Vivek. "Power Analysis and Optimization from Circuit to Register-Transfer Levels". In EDA for IC Implementation, Circuit Design, and Process Technology, edited by Lavagno, Luciano; Scheffer, Louis; Grant, Martin. CRC Press, 2006.
    Published • 10.1201/9781420007954-3
Conference paper
  1. Korakitis, Orestis; De Gonzalo, Simon Garcia; Guidotti, Nicolas; Barreto, João; Monteiro, José; Pena, A.. Corresponding author: Korakitis, Orestis. "OmpSs-2 and OpenACC Interoperation". Paper presented in Ninth Workshop on Accelerator Programming Using Directives, 2022.
    Published
  2. Korakitis, Orestis; De Gonzalo, Simon Garcia; Guidotti, Nicolas; Barreto, João Pedro; Monteiro, José; Peña, Antonio J.. "Towards OmpSs-2 and OpenACC Interoperation". Paper presented in Symposium on Principles and Practice of Parallel Programming, 2022.
    Published • 10.1145/3503221.3508401
  3. Guidotti, Nicolas; Ceyrat, Pedro; Barreto, João; Monteiro, José; Rodrigues, Rodrigo (8F14-9CDA-FFD6); Fonseca, Ricardo; Martorell, Xavier; Peña, Antonio. "Particle-In-Cell Simulation using Asynchronous Tasking". Paper presented in 27th International European Conference on Parallel and Distributed Computing (Euro-Par 21), Lisboa, 2021.
    Accepted
  4. Iakymchuk, Roman; Faustino, Amândio; Emerson, Andrew; Barreto, João; Bartsch, Valeria; Rodrigues, Rodrigo (8F14-9CDA-FFD6); Monteiro, José. "Efficient and Eventually Consistent Collective Operations". Paper presented in Advances in Parallel and Distributed Computational Models, 2021.
    Accepted
  5. Santos, Rafael; Afonso, João; Monteiro, José. "Short-circuit Analysis using a Parallel QBF Solver". Paper presented in XXXV Conference on Design of Circuits and Integrated Systems (DCIS 2020), Segovia, 2020.
    Published
  6. Madeira, Dinis; Monteiro, José; Duarte, Rui (B91E-770F-19A3). "Specification and Implementation of the Didactic Processor P4 and Its Development Environment". Paper presented in REC2020 - XVI Jornadas sobre Sistemas Reconfiguráveis, Lisboa, 2020.
    Published
  7. Liacha, Ahmed; Oudjida, Abdelkrim; Ferguene, Farid; Monteiro, José; Flores, Paulo. "A variable radix-2^r algorithm for single constant multiplication". Paper presented in 15th IEEE International New Circuits and Systems Conference, NEWCAS 2017, Strasbourg, 2017.
    10.1109/newcas.2017.8010156
  8. Afonso, João; Monteiro, José. "Analysis of short-circuit conditions in logic circuits". Paper presented in Design, Automation Test in Europe Conference Exhibition (DATE), 2017, Lausanne, 2017.
    Published • 10.23919/DATE.2017.7927102
  9. Aksoy, Levent; Flores, Paulo; Monteiro, José. "A novel method for the approximation of multiplierless constant matrix vector multiplication". Paper presented in IEEE 13th International Conference on Embedded and Ubiquitous Computing, Porto, 2015.
    Published • 10.1109/EUC.2015.27
  10. Aksoy, Levent; Flores, Paulo; Monteiro, José. "Approximation of multiple constant multiplications using minimum look-up tables on FPGA". Paper presented in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015.
    Published • 10.1109/ISCAS.2015.7169289
  11. Aksoy, Levent; Flores, Paulo; Monteiro, José. "Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA". Paper presented in IEEE 32nd International Conference on Computer Design, ICCD 2014, Seul, 2014.
    Published • 10.1109/iccd.2014.6974660
  12. Aksoy, Levent; Flores, Paulo; Monteiro, José. "ECHO: A novel method for the multiplierless design of constant array vector multiplication". Paper presented in IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, 2014.
    Published • 10.1109/iscas.2014.6865420
  13. Aksoy, Levent; Flores, Paulo; Monteiro, José. "Optimization of design complexity in time-multiplexed constant multiplications". Paper presented in Design, Automation Test in Europe Conference Exhibition, DATE 2014, Dresden, 2014.
    Published • 10.7873/DATE.2014.313
  14. Lopes, Nuno; Monteiro, José. "Weakest precondition synthesis for compiler optimizations". Paper presented in 15th International Conference on Verification, Model Checking, and Abstract Interpretation, VMCAI 2014, San Diego, CA, 2014.
    Published
  15. Aksoy, Levent; Flores, Paulo; Monteiro, José. "Towards the least complex time-multiplexed constant multiplication". Paper presented in IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-Soc 2013, Istanbul, 2013.
    Published • 10.1109/VLSI-SoC.2013.6673302
  16. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Exploration of tradeoffs in the design of integer cosine transforms for image compression". Paper presented in European Conference on Circuit Theory and Design, ECCTD 2013, Dresden, 2013.
    Published • 10.1109/ECCTD.2013.6662223
  17. Pieper, Leandro; Costa, Eduardo; Monteiro, José. "Combination of radix-2^m multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers". Paper presented in 26th Symposium on Integrated Circuits and Systems Design, SBCCI 2013, Curitiba, 2013.
    Published • 10.1109/sbcci.2013.6644866
  18. Lopes, Nuno; Monteiro, José. "Automatic equivalence checking of UF+IA programs". Paper presented in International SPIN Symposium on Model Checking of Software - SPIN13, Stony Brook, 2013.
    Published • 10.1007/978-3-642-39176-7-18
  19. Brito, Diogo; Fernandes, Jorge; Flores, Paulo; Monteiro, José. "Standard CMOS voltage-mode QLUT using a clock boosting technique". Paper presented in 2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013, Paris, 2013.
    Published • 10.1109/NEWCAS.2013.6573573
  20. Aksoy, Levent; Flores, Paulo; Monteiro, José. "SIREN: a depth-first search algorithm for the filter design optimization problem". Paper presented in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, Paris, 2013.
    Published • 10.1145/2483028.2483087
  21. Brito, Diogo; Fernandes, Jorge; Flores, Paulo; Monteiro, José. "Design and characterization of a QLUT in a standard CMOS process". Paper presented in 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, Sevilla, 2012.
    Published • 10.1109/ICECS.2012.6463744
  22. Ghissoni, Sidinei; Costa, Eduardo; Monteiro, José; Reis, Ricardo. "Efficient area and power multiplication part of FFT based on twiddle factor decomposition". Paper presented in 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, Sevilla, 2012.
    Published • 10.1109/ICECS.2012.6463640
  23. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Multiple tunable constant multiplications: Algorithms and applications". Paper presented in IEEE/ACM International Conference on Computer-Aided Design, ICCAD, San Jose, CA, 2012.
    Published
  24. Bispo, João (121D-D25C-4FAE); Cardoso, João; Monteiro, José. "Hardware pipelining of runtime-detected loops". Paper presented in IEEE 25th Symposium on Integrated Circuits and Systems Design, SBCCI 2012, Brasília, 2012.
    Published
  25. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Design of low-complexity digital finite impulse response filters on FPGAs". Paper presented in IEEE/ACM Design, Automation and Test in Europe, DATE, Dresden, 2012.
    Published
  26. Ghissoni, Sidinei; Costa, Eduardo; Monteiro, José; Reis, Ricardo. "Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization". Paper presented in 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, Beirute, 2011.
    Published • 10.1109/ICECS.2011.6122338
  27. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "A hybrid algorithm for the optimization of area and delay in linear DSP transforms". Paper presented in IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, 2011.
    Published • 10.1109/VLSISoC.2011.6081637
  28. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Optimization of gate-level area in high throughput multiple constant multiplications". Paper presented in 20th European Conference on Circuit Theory and Design, ECCTD 2011, Linkoping, 2011.
    Published • 10.1109/ECCTD.2011.6043602
  29. Aksoy, Levent; Lazzari, Cristiano; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Efficient shift-adds design of digit-serial multiple constant multiplications". Paper presented in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, Lausanne, 2011.
    Published • 10.1145/1973009.1973023
  30. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Design of low-power multiple constant multiplications using low-complexity minimum depth operations". Paper presented in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, Lausanne, 2011.
    Published • 10.1145/1973009.1973026
  31. Oliveira, Leonardo; Dessbesell, Gustavo; Martins, João; Monteiro, José. "Hardware implementation of a centroid-based localization algorithm for mobile sensor networks". Paper presented in IEEE International Symposium on Circuits and Systems - ISCAS, Rio de Janeiro, 2011.
    Published • 10.1109/ISCAS.2011.5938194
  32. Aksoy, Levent; Lazzari, Cristiano; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Optimization of area in digit-serial Multiple Constant Multiplications at gate-level". Paper presented in IEEE International Symposium of Circuits and Systems, ISCAS 2011, Rio de Janeiro, 2011.
    Published • 10.1109/iscas.2011.5938171
  33. Ghissoni, Sidinei; Costa, Eduardo; Lazzari, Cristiano; Monteiro, José; Aksoy, Levent; Reis, Ricardo. "Radix-2 Decimation in Time (DIT) FFT implementation based on a matrix-multiple constant multiplication approach". Paper presented in IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Atenas, 2010.
    Published • 10.1109/ICECS.2010.5724648
  34. Lazzari, Cristiano; Fernandes, Jorge; Flores, Paulo; Monteiro, José. "An efficient low power multiple-value look-up table targeting quaternary FPGAs". Paper presented in International Workshop on Power and Timing Modeling, Optimization and Simulation - PATMOS, Grenoble, 2010.
    Published • 10.1007/978-3-642-17752-1-9
  35. Jaccottet, Diego; Costa, Eduardo; Aksoy, Levent; Flores, Paulo; Monteiro, José. "Design of low-complexity and high-speed digital finite impulse response filters". Paper presented in 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010, Madrid, 2010.
    Published • 10.1109/VLSISOC.2010.5642676
  36. Oliveira, Leonardo; Martins, João; Dessbesell, Gustavo; Monteiro, José. "CentroidM: A Centroid-based localization algorithm for mobile sensor networks". Paper presented in 23rd Symposium on Integrated Circuits and Systems Design, SBCCI'10, São Paulo, 2010.
    Published • 10.1145/1854153.1854203
  37. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Optimization of area and delay at gate-level in Multiple Constant Multiplications". Paper presented in 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010, Lile, 2010.
    Published • 10.1109/DSD.2010.32
  38. Lazzari, Cristiano; Flores, Paulo; Monteiro, José; Carro, Luigi. "A new quaternary FPGA based on a voltage-mode multi-valued circuit". Paper presented in IEEE/ACM Design, Automation and Test in Europe, DATE, Dresden, 2010.
    Published
  39. Lazzari, Cristiano; Flores, Paulo; Monteiro, José. "Voltage-mode quaternary FPGAs: An evaluation of interconnections". Paper presented in IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, 2010.
    Published • 10.1109/ISCAS.2010.5537423
  40. Sampaio, Carlos; Monteiro, José; Silveira, L. Miguel. "Analysis of the conditions for worst case switching activity in integrated circuits". Paper presented in 1st IEEE Latin American Symposium on Circuits and Systems, LASCAS 2010, Iguaçu, 2010.
    Published • 10.1109/lascas.2010.7410234
  41. Lazzari, Cristiano; Flores, Paulo; Monteiro, José. "Power and delay comparison of binary and quaternary arithmetic circuits". Paper presented in 3rd International Conference on Signals, Circuits and Systems, SCS 2009, Jerba, 2009.
    Published • 10.1109/ICSCS.2009.5412586
  42. Costa, Jose; Monteiro, José. "Observability-based coverage-directed path search using PBO for automatic test vector generation". Paper presented in 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianópolis, 2009.
    Published • 10.1109/VLSISOC.2009.6041346
  43. Gusmão, Alexandre; Silveira, L. Miguel; Monteiro, José. "Power macro-modelling using an iterative LS-SVM method". Paper presented in 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianópolis, 2009.
    Published • 10.1109/VLSISOC.2009.6041324
  44. Ghissoni, Sidinei; Martins, João; Reis, Ricardo; Monteiro, José. "Analysis of power consumption using a new methodology for the capacitance modeling of complex logic gates". Paper presented in International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009, Delft, 2009.
    Published • 10.1007/978-3-642-11802-9_34
  45. Costa, José; Monteiro, José. "A MILP-based approach to path sensitization of embedded software". Paper presented in Design, Automation and Test in Europe, DATE 2009, Nice, 2009.
    10.1109/date.2009.5090913
  46. Gusmão, António; Silveira, L. Miguel; Monteiro, José. "Parameter tuning in SVM-based power macro-modeling". Paper presented in 10th International Symposium on Quality Electronic Design, ISQED 2009, San Jose, CA, 2009.
    Published • 10.1109/ISQED.2009.4810283
  47. Pieper, Leandro; Costa, Eduardo; Almeida, Sérgio; Bampi, Sérgio; Monteiro, José. "Efficient dedicated multiplication blocks for 2's complement radix-16 and radix-256 array multipliers". Paper presented in 2nd International Conference on Signals, Circuits and Systems, SCS 2008, Hammamet, 2008.
    Published • 10.1109/ICSCS.2008.4746936
  48. Morgado, Pedro; Flores, Paulo; Monteiro, José; Silveira, L. Miguel. "Generating worst-case stimuli for accurate power grid analysis". Paper presented in International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS, Lisboa, 2008.
    Published • 10.1007/978-3-540-95948-9_25
  49. Costa, José; Monteiro, José. "Computation of the minimal set of paths for observability-based statement coverage". Paper presented in 15th International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2008, Poznan, 2008.
    Published
  50. Aksoy, Levent; Gunes, Ece; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Effect of number representation on the achievable minimum number of operations in multiple constant multiplications". Paper presented in IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, Shangai, 2007.
    Published • 10.1109/SIPS.2007.4387585
  51. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Minimum number of operations under a general number representation for digital filter synthesis". Paper presented in European Conference on Circuit Theory and Design, ECCTD 2007, Sevilla, 2007.
    Published • 10.1109/ECCTD.2007.4529584
  52. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Optimization of area in digital FIR filters using gate-level metrics". Paper presented in 44th Design Automation Conference, DAC, San Diego, CA, 2007.
    Published • 10.1109/DAC.2007.375200
  53. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "ASSUMEs: Heuristic algorithms for optimization of area and delay in digital filter synthesis". Paper presented in IEEE International Conference on Electronics, Circuits, and Systems, ICECS, Nice, 2006.
    Published • 10.1109/ICECS.2006.379897
  54. Costa, Eduardo; Flores, Paulo; Monteiro, José. "Exploiting general coefficient representation for the optimal sharing of partial products in MCMs". Paper presented in 19th Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, 2006.
    Published
  55. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming". Paper presented in Design Automation Conference, DAC 2006, San Francisco, CA, 2006.
    Published • 10.1145/1146909.1147079
  56. Flores, Paulo; Monteiro, José; Costa, Eduardo. "An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications". Paper presented in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, San Jose, CA, 2005.
    Published • 10.1109/ICCAD.2005.1560032
  57. Monteiro, José; Fernandes, Jorge; Silveira, L. Miguel. "A case for a triangular waveform clock signal". Paper presented in IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2005, Perth, 2005.
    Published
  58. Oliveira, Leonardo; Santos, Cristiano; Ferrão, Daniel; Costa, Eduardo; Monteiro, José; Martins, João; Bampi, Sérgio; Reis, Ricardo. "A comparison of layout implementations of pipelined and non-pipelined signed radix-4 array multiplier and modified Booth multiplier architectures". Paper presented in IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2005, Perth, 2005.
    Published
  59. Costa, Eduardo; Flores, Paulo; Monteiro, José. "Maximal sharing of partial terms in MCM under minimal signed digit representation". Paper presented in European Conference on Circuit Theory and Design, ECCTD 2005, Cork, 2005.
    Published • 10.1109/ECCTD.2005.1523033
  60. Fonseca, Marcelo; Bampi, S.; Costa, Eduardo; Monteiro, José. "Design of a radix-2^m Hybrid array multiplier using carry save adders". Paper presented in 18th Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianópolis, 2005.
    Published • 10.1109/SBCCI.2005.4286852
  61. Rosa, Vagner; Costa, Eduardo; Monteiro, José; Bampi, Sérgio. "Performance evaluation of parallel FIR filter optimizations in ASICs and FPGA". Paper presented in Midwest Symposium on Circuits and Systems, MWSCAS 2005, Cincinnati, 2005.
    Published • 10.1109/MWSCAS.2005.1594393
  62. Fonseca, Marcelo; Costa, Eduardo; Bampi, Sérgio; Monteiro, José. "Performance optimization of radix-2^n multipliers using carry save adders". Paper presented in Iberchip, São Salvador, 2005.
    Published
  63. Rosa, Vagner; Costa, Eduardo; Monteiro, José; Bampi, Sérgio. "An improved synthesis method for low power hardwired FIR filters". Paper presented in 17th Symposium on Integrated Cicuits and Systems Design, SBCCI 2004, Porto Galinhas, 2004.
    Published
  64. Oliveira, Leonardo; Martins, João; Costa, Eduardo; Bampi, Sérgio; Monteiro, José. "Array hybrid multiplier versus modified Booth multiplier: comparing area and power consumption of layout implementations of signed radix-4 architectures". Paper presented in Midwest Symposium on Circuits and Systems, MWSCAS 2004, Hiroshima, 2004.
    Published
  65. Costa, Eduardo; Monteiro, José; Bampi, Sérgio. "Gray encoded arithmetic operators applied to FFT and FIR dedicated datapaths". Paper presented in Twelfth International Conference on Very Large Scale Integration of System on Chip, VLSI-SoC 2003, Darmstadt, 2003.
    Published • 10.1007/0-387-33403-3_18
  66. Costa, Eduardo; Bampi, Sérgio; Monteiro, José. "Low power architectures for FFT and FIR dedicated datapaths". Paper presented in 46th Midwest Symposium on Circuits and Systems, MWSCAS 2003, Cairo, 2003.
    Published • 10.1109/mwscas.2003.1562584
  67. Costa, Eduardo; Bampi, Sérgio; Monteiro, José. "A new pipelined array architecture for signed multiplication". Paper presented in 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003, São Paulo, 2003.
    Published • 10.1109/sbcci.2003.1232808
  68. Portela, João; Costa, Eduardo; Monteiro, José. "Optimal combination of number of taps and coefficient bit-width for low power FIR filter realization". Paper presented in IEEE European Conference on Circuit Theory and Design, ECCTD 2003, Krakow, 2003.
    Published
  69. Costa, Eduardo; Bampi, Sérgio; Monteiro, José. "A new architecture for signed radix-2^m pure array multipliers". Paper presented in IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2002, Freiburg, 2002.
    Published
  70. Costa, Eduardo; Bampi, Sérgio; Monteiro, José. "A new architecture for 2's complement Gray encoded array multiplier". Paper presented in 15th Symposium on Integrated Circuits and Systems Design, SBCCI 2002, Porto Alegre, 2002.
    Published • 10.1109/sbcci.2002.1137631
  71. Costa, Eduardo; Bampi, Sérgio; Monteiro, José. "FIR filter design using low power arithmetic operators". Paper presented in EEE 5th Design and Diagnostics of Electronic Circuits and Systems, DDECS 2002, Brno, 2002.
    Published
  72. Costa, Eduardo; Bampi, Sérgio; Monteiro, José. "Power efficient arithmetic operand encoding". Paper presented in 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001, Brasília, 2001.
    Published • 10.1109/sbcci.2001.953027
  73. Portela, João; Monteiro, José. "Power optimized Viterbi decoder implementation through architectural transforms". Paper presented in 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001, Brasília, 2001.
    Published • 10.1109/sbcci.2001.953029
  74. Costa, Eduardo; Bampi, Sérgio; Monteiro, José. "Power optimization using coding methods on arithmetic operators". Paper presented in IEEE International Symposium on Signals, Circuits and Systems, SCS 2001, Iasi, 2001.
    Published
  75. Costa, José; Devadas, Srinivas; Monteiro, José. "Observability analysis of embedded software for coverage-directed validation". Paper presented in IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2000, San Jose, CA, 2000.
    Published
  76. Martins, João; Reis, Ricardo; Monteiro, José. "Capacitance and power modeling at the logic level". Paper presented in IFIP International Conference on Chip Design Automation, Beijing, 2000.
    Published
  77. Ferreira, Ricardo; Trullemans, A.-M.; Costa, Jose; Monteiro, José. "Probabilistic bottom-up RTL power estimation". Paper presented in IEEE First International Symposium on Quality Electronic Design, ISQED 2000, San Jose, CA, 2000.
    Published • 10.1109/isqed.2000.838916
  78. Monteiro, José; Oliveira, Arlindo. "FSM decomposition by direct circuit manipulation applied to low power design". Paper presented in Asia and South Pacific Design Automation Conference, ASP-DAC 2000, Yokohama, 2000.
    Published • 10.1145/368434.368678
  79. Mota, Antonio; Ferreira, Nuno; Oliveira, Arlindo; Monteiro, José. "Integrating Dynamic Power Management in the Design Flow". Paper presented in IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip, VLSI-SoC 1999, Lisboa, 1999.
    Published
  80. Freitas, Ana Teresa; Oliveira, Arlindo; Monteiro, José. "Exact Power Estimation Using Word Level Transition Probabilities". Paper presented in Ninth International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 1999, Kos, 1999.
    Published
  81. Monteiro, José. "Power optimization using dynamic power management". Paper presented in XII Symposium on Integrated Circuits and Systems Design, SBCCI 1999, Natal, 1999.
    Published • 10.1109/sbcci.1999.803105
  82. Costa, José; Monteiro, José; Silveira, L. Miguel; Devadas, Srinivas. "A probabilistic approach for RT-level power modeling". Paper presented in 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Paphos, 1999.
    Published • 10.1109/icecs.1999.813262
  83. Costa, José; Silveira, L. Miguel; Monteiro, José. "Sequential power estimation using probability polynomials". Paper presented in IEEE International Symposium on Signals, Circuits and Systems, SCS 1999, Iasi, 1999.
    Published
  84. Flores, Paulo; Costa, José; Neto, Horácio; Monteiro, José; Marques-Silva, João. "Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation". Paper presented in IEEE International Conference on VLSI Design, Goa, 1999.
    Published
  85. Monteiro, José. "Techniques for power management at the logic level". Paper presented in IEEE International Conference on Electronics, Circuits, and Systems, ICECS 1998, Lisboa, 1998.
    Published
  86. Monteiro, José; Oliveira, Arlindo. "Finite state machine decomposition for low power". Paper presented in 35th Design Automation Conference, DAC 1998, San Francisco, CA, 1998.
    Published
  87. Mota, António; Monteiro, José; Oliveira, Arlindo. "Power optimization of combinational modules using self-timed precomputation". Paper presented in IEEE International Symposium on Circuits and Systems, ISCAS, Monterey, CA, 1998.
    Published
  88. Costa, José; Flores, Paulo; Monteiro, José; Marques-Silva, João. "Exploiting don’t cares in test patterns to reduce power during BIST". Paper presented in IEEE European Test Workshop, ETW 1998, Sitges, 1998.
    Published
  89. Costa, José; Monteiro, José; Devadas, Srinivas. "Switching activity estimation using limited depth reconvergent path analysis". Paper presented in International Symposium on Low Power Electronics and Design, Digest of Technical Papers, ISLPED, Monterey, CA, 1997.
    Published
  90. Monteiro, José; Marques-Silva, João. "Testability analysis of circuits using data-dependent power". Paper presented in IX IFIP International Conference on Very Large Scale Integration, VLSI 1997, Gramado, 1997.
    Published
  91. Marques-Silva, João; Monteiro, José; Sakallah, Karem. "Test pattern generation for circuits using power management techniques". Paper presented in IEEE European Test Workshop, ETW 1997, Cagliari, 1997.
    Published
  92. Monteiro, José; Devadas, Srinivas; Ashar, Pranav; Mauskar, Ashutosh. "Scheduling techniques to enable power management". Paper presented in 33rd Design Automation Conference, DAC 1996, Las Vegas, NV, 1996.
    Published
  93. Monteiro, José; Devadas, Srinivas. "Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs". Paper presented in International Symposium on Low Power Electronics Design, ISLPED, Laguna Beach, CA, 1995.
    Published
  94. Monteiro, José; Rinderknecht, John; Devadas, Srinivas; Ghosh, Abhijit. "Optimization of combinational and sequential logic circuits for low power using precomputation". Paper presented in 16th Conference on Advanced Research in VLSI, Chapel Hill, NC, 1995.
    Published • 10.1109/arvlsi.1995.515637
  95. Alidina, Mazhar; Monteiro, José; Devadas, Srinivas; Ghosh, Abhijit; Papefthymiou, Marios. "Precomputation-based sequential logic optimization for low power". Paper presented in IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, CA, 1994.
    Published • 10.1109/iccad.1994.629747
  96. Monteiro, José; Devadas, Srinivas; Lin, Bill. "Methodology for efficient estimation of switching activity in sequential logic circuits". Paper presented in 31st Design Automation Conference, DAC 1994, San Diego, CA, 1994.
    Published
  97. Monteiro, José; Kukula, James; Devadas, Srinivas. "Bitwise encoding of finite state machines". Paper presented in IEEE International Conference on VLSI Design, Calcutta, 1994.
    Published
  98. Monteiro, José; Devadas, Srinivas; Ghosh, Abhijit. "Retiming sequential circuits for low power". Paper presented in International Conference on Computer Aided Design, ICCAD 1993, Santa Clara, CA, 1993.
    Published • 10.1109/ICCAD.1993.580087
Edited book
  1. Monteiro, José; Van Leuken, Rene. Corresponding author: Monteiro, José. Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation: 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers. Springer. 2010.
    Published
  2. Monteiro, José; Svensson, Lars. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Springer Berlin Heidelberg. 2009.
    Published • 10.1007/978-3-540-95948-9 • Editor
Journal article
  1. Leonardo L. de Oliveira; Gabriel H. Eisenkraemer; Everton A. Carara; João B. Martins; Monteiro, José. "Mobile Localization Techniques for Wireless Sensor Networks: Survey and Recommendations". ACM Transactions on Sensor Networks (2022): http://dx.doi.org/10.1145/3561512.
    10.1145/3561512
  2. Cruz, Helena; Véstias, Mário; Monteiro, José; Neto, Horácio; Duarte, Rui Policarpo. Corresponding author: Véstias, Mário. "A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective". Remote Sensing 14 5 (2022): 1258. http://dx.doi.org/10.3390/rs14051258.
    Open access • Accepted • 10.3390/rs14051258
  3. Filipe Magalhães; José Monteiro; Juan A. Acebrón; José R. Herrero. "A distributed Monte Carlo based linear algebra solver applied to the analysis of large complex networks". Future Generation Computer Systems 127 (2022): 320-330. https://doi.org/10.1016/j.future.2021.09.014.
    10.1016/j.future.2021.09.014
  4. Liacha, Ahmed; Oudjida, Abdelkrim K.; Bakiri, Mohammed; Monteiro, José; Flores, Paulo. "Radix-2^r recoding with common subexpression elimination for multiple constant multiplication". IET Circuits, Devices & Systems 14 7 (2020): 990-994. http://dx.doi.org/10.1049/iet-cds.2020.0213.
    Published • 10.1049/iet-cds.2020.0213
  5. Juan A. Acebrón; José R. Herrero; José Monteiro. "A highly parallel algorithm for computing the action of a matrix exponential on a vector based on a multilevel Monte Carlo method". Computers & Mathematics with Applications 79 12 (2020): 3495-3515. https://doi.org/10.1016/j.camwa.2020.02.013.
    10.1016/j.camwa.2020.02.013
  6. Aksoy, Levent; Flores, Paulo; Monteiro, José. "A novel method for the approximation of multiplierless constant matrix vector multiplication". EURASIP Journal on Embedded Systems 2016 1 (2016): 1-11. http://dx.doi.org/10.1186/s13639-016-0033-y.
    Published • 10.1109/EUC.2015.27
  7. Lopes, Nuno; Monteiro, José. "Automatic equivalence checking of programs with uninterpreted functions and integer arithmetic". International Journal on Software Tools for Technology Transfer 18 4 (2015): 359-374. http://dx.doi.org/10.1007/s10009-015-0366-1.
    Published • 10.1007/s10009-015-0366-1
  8. Brito, Diogo; Rabuske, Taimur; Fernandes, Jorge; Flores, Paulo; Monteiro, José. "Quaternary logic lookup table in standard CMOS". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 2 (2015): 306-316. http://dx.doi.org/10.1109/tvlsi.2014.2308302.
    Published • 10.1109/tvlsi.2014.2308302
  9. Aksoy, Levent; Flores, Paulo; Monteiro, José. "Exact and Approximate Algorithms for the Filter Design Optimization Problem". IEEE Transactions on Signal Processing 63 1 (2015): 142-154. http://dx.doi.org/10.1109/tsp.2014.2366713.
    Published • 10.1109/tsp.2014.2366713
  10. Aksoy, Levent; Flores, Paulo; Monteiro, José. "Multiplierless Design of Folded DSP Blocks". ACM Transactions on Design Automation of Electronic Systems 20 1 (2014): 1-24. http://dx.doi.org/10.1145/2663343.
    Published • 10.1145/2663343
  11. Aksoy, Levent; Flores, Paulo; Monteiro, José. "A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures". Circuits, Systems, and Signal Processing 33 6 (2014): 1689-1719. http://dx.doi.org/10.1007/s00034-013-9727-8.
    Published • 10.1007/s00034-013-9727-8
  12. Costa, José; Monteiro, José. "Coverage-directed observability-based validation for embedded software". ACM Transactions on Design Automation of Electronic Systems 18 2 (2013): 19:1-19:20. http://www.scopus.com/inward/record.url?eid=2-s2.0-84878476084&partnerID=MN8TOARS.
    Published • 10.1145/2442087.2442090
  13. BISPO, JOÃO; Cardoso, João; Monteiro, José. "Hardware pipelining of repetitive patterns in processor instruction traces". Journal of Integrated Circuits and Systems 8 1 (2013): 22-31. http://www.scopus.com/inward/record.url?eid=2-s2.0-84885355741&partnerID=MN8TOARS.
    Published
  14. Aksoy, Levent; Lazzari, Cristiano; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Design of digit-serial FIR filters: algorithms, architectures, and a CAD tool". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 3 (2013): 498-511. http://www.scopus.com/inward/record.url?eid=2-s2.0-84874646348&partnerID=MN8TOARS.
    Published • 10.1109/TVLSI.2012.2188917
  15. Aksoy, Levent; Lazzari, Cristiano; Costa, Eduardo; Flores, Paulo; Monteiro, José. "High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications". Integration, the VLSI Journal 45 3 (2012): 294-306. http://www.scopus.com/inward/record.url?eid=2-s2.0-84860516076&partnerID=MN8TOARS.
    Published • 10.1016/j.vlsi.2011.11.008
  16. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Optimization algorithms for the multiplierless realization of linear transforms". ACM Transactions on Design Automation of Electronic Systems 17 1 (2012): 3:1-3:27. http://www.scopus.com/inward/record.url?eid=2-s2.0-84857851929&partnerID=MN8TOARS.
    Published • 10.1145/2071356.2071359
  17. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Finding the optimal tradeoff between area and delay in multiple constant multiplications". Microprocessors and Microsystems 35 8 (2011): 729-741. http://www.scopus.com/inward/record.url?eid=2-s2.0-81855225340&partnerID=MN8TOARS.
    Published • 10.1016/j.micpro.2011.08.009
  18. Sampaio, Carlos; Monteiro, José; Silveira, L. Miguel. "Analysis of the conditions for the worst case switching activity in integrated circuits". Analog Integrated Circuits and Signal Processing 70 2 (2011): 229-240. http://dx.doi.org/10.1007/s10470-011-9782-7.
    Published • 10.1007/s10470-011-9782-7
  19. Lazzari, Cristiano; Fernandes, Jorge; Flores, Paulo; Monteiro, José. "Low power multiple-value voltage-mode look-up table for quaternary field programmable gate arrays". Journal of Low Power Electronics 7 2 (2011): 294-301. http://www.scopus.com/inward/record.url?eid=2-s2.0-84856970656&partnerID=MN8TOARS.
    Published • 10.1166/jolpe.2011.1138
  20. Pieper, Leandro; Costa, Eduardo; Almeida, Sérgio; Bampi, Sérgio; Monteiro, José. "Efficient dedicated multiplication blocks for 2's complement radix-2^m array multipliers". Journal of Computers 5 10 (2010): 1502-1509. http://www.scopus.com/inward/record.url?eid=2-s2.0-78651592903&partnerID=MN8TOARS.
    10.4304/jcp.5.10.1502-1509
  21. Aksoy, Levent; Costa, Eduardo; Flores, Paulo; Monteiro, José. "Exact and approximate algorithms for the optimization of area and delay in multiple constant multiplications". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27 6 (2008): 1013-1026. http://www.scopus.com/inward/record.url?eid=2-s2.0-44149085203&partnerID=MN8TOARS.
    Published • 10.1109/TCAD.2008.923242
  22. Costa, Eduardo; Monteiro, José; Bampi, Sérgio. "A new array architecture for signed multiplication using Gray encoded radix-2^m operands". Integration, the VLSI Journal 40 2 (2007): 118-132. http://www.scopus.com/inward/record.url?eid=2-s2.0-33751526018&partnerID=MN8TOARS.
    Published • 10.1016/j.vlsi.2006.02.010
  23. Costa, Jose; Silveira, L. Miguel; Devadas, Srinivas; Monteiro, José. "Power estimation using probability polynomials". Design Automation for Embedded Systems 9 1 (2005): 19-52. http://www.scopus.com/inward/record.url?eid=2-s2.0-17444421573&partnerID=MN8TOARS.
    Published • 10.1007/s10617-005-5344-5
  24. Monteiro, José; Oliveira, Arlindo. "Implicit FSM decomposition applied to low-power design". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10 5 (2002): 560-565. http://www.scopus.com/inward/record.url?eid=2-s2.0-0036818380&partnerID=MN8TOARS.
    Published • 10.1109/TVLSI.2002.801611
  25. Monteiro, José; Devadas, Srinivas. "Power estimation under user-specified input sequences and programs". Integrated Computer-Aided Engineering 5 2 (1998): 177-185. http://www.scopus.com/inward/record.url?eid=2-s2.0-0031650469&partnerID=MN8TOARS.
    Published
  26. Monteiro, José; Devadas, Srinivas. "Sequential logic optimization for low power using input-disabling precomputation architectures". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17 3 (1998): 279-284. http://www.scopus.com/inward/record.url?eid=2-s2.0-0003017407&partnerID=MN8TOARS.
    Published • 10.1109/43.700725
  27. Monteiro, José; Devadas, Srinivas; Ghosh, Abhijit; Keutzer, Kurt; White, Jacob. "Estimation of average switching activity in combinational logic circuits using symbolic simulation". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16 1 (1997): 121-127. http://www.scopus.com/inward/record.url?eid=2-s2.0-0030650441&partnerID=MN8TOARS.
    Published • 10.1109/43.559336
  28. Monteiro, José; Devadas, Srinivas; Ghosh, Abhijit. "Retiming Sequential Circuits for Low Power". International Journal of High Speed Electronics and Systems 07 02 (1996): 323-340. http://dx.doi.org/10.1142/s0129156496000141.
    Published • 10.1142/s0129156496000141
  29. Monteiro, José; Devadas, Srinivas. "Techniques for power estimation and optimization at the logic level: a survey". Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 13 2-3 (1996): 259-276. http://www.scopus.com/inward/record.url?eid=2-s2.0-0030206110&partnerID=MN8TOARS.
    Published
  30. Tsui, Chi-Ying; Monteiro, José; Pedram, Massoud; Devadas, Srinivas; Despain, Alvin; Lin, Bill. "Power estimation methods for sequential logic circuits". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3 3 (1995): 404-416. http://www.scopus.com/inward/record.url?eid=2-s2.0-0029379466&partnerID=MN8TOARS.
    Published • 10.1109/92.406998
  31. Alidina, Mazhar; Monteiro, José; Devadas, Srinivas; Ghosh, Abhijit; Papaefthymiou, Marios. "Precomputation-based sequential logic optimization for low power". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2 4 (1994): 426-436.
    Published • 10.1109/92.335011
Preface / Postscript
  1. Monteiro, José; Van Leuken, Rene. "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics): Preface". Preface to Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2010.
    Published
  2. Monteiro, José; Svensson, Lars. "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics): Preface". Preface to Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics): Preface. Springer Berlin Heidelberg. 1998.
    Published • Editor
Preprint
  1. Helena Cruz; Paulo Flores; Mário Véstias; José Monteiro; Horácio Neto; Rui Policarpo Duarte. "Algorithm-Specific Optimizations for On-Board Real-Time Backprojection on FPGA". 2023. https://doi.org/10.20944/preprints202312.0640.v1.
    10.20944/preprints202312.0640.v1
Thesis / Dissertation
  1. Monteiro, José. "A Computer-Aided Design Methodology for Low Power Sequential Logic Circuits". PhD, Massachusetts Institute of Technology, 1996. https://www.inesc-id.pt/ficheiros/publicacoes/1829.pdf.
  2. Monteiro, José. "Codificação de Máquinas de Estados em Síntese Automática de Circuitos Lógicos". Master, Universidade de Lisboa Instituto Superior Técnico, 1992.

Intellectual property

Patent
  1. Fernandes, Jorge; Lazzari, Cristiano; Flores, Paulo; Monteiro, José. 2011. "Tabela Multi-Valor para Dispositivos Lógicos Programáveis". Portugal.
    Granted/Issued
Activities

Event organisation

Event name
Type of event (Role) 		Institution / Organization
2009 - Current Power and Timing Modeling, Optimization and Simulation PATMOS (2009)
Conference (Member of the Scientific Committee)
2008 - Current Steering Committee Member PATMOS (2008)
Conference (Member of the Organising Committee)
1999 - Current IEEE Symposium on Integrated Circuits and Systems Design SBCCI (1999)
Conference (Member of the Scientific Committee)
2014 - 2019 IEEE Latin American Symposium on Circuits and Systems LASCAS (2014)
Conference (Member of the Scientific Committee)
2012 - 2019 IEEE/ACM Design, Automation and Test in Europe (2012/03)
Conference (Member of the Scientific Committee)
2017 - 2018 IFIP/IEEE International Conference on Very Large Scale Integration (2017)
Conference (Member of the Scientific Committee)
2017 - 2017 Publications Chair, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (2017/10)
Conference (Member of the Organising Committee)
2015 - 2016 IEEE International Conference on Computer Design ICCD (2015)
Conference (Member of the Scientific Committee)
2015 - 2016 IEEE International Conference on Electronics, Circuits and Systems ICECS (2015)
Conference (Member of the Scientific Committee)
2014 - 2016 IEEE/ACM Design Automation Conference DAC (2014/06)
Conference (Member of the Scientific Committee)
2013 - 2015 Track-chair, IEEE/ACM Design, Automation and Test in Europe (2013/03 - 2015)
Conference (Member of the Organising Committee)
2010 - 2011 IEEE International Conference NEWCAS (2010)
Conference (Member of the Scientific Committee)
2009 - 2009 Program Chair, Power And Timing Modeling, Optimization and Simulation PATMOS’09 (2009/09)
Conference (Member of the Organising Committee)
2008 - 2008 General Chair, Power And Timing Mode- ling, Optimization and Simulation PATMOS’08 (2008/09)
Conference (President of the Organising Committee)
1999 - 2001 IEEE International Workshop on Logic Synthesis IWLS (1999)
Conference (Member of the Scientific Committee)
2000 - 2000 Program Chair, XIII Symposium on Integrated Circuits and Systems Design SBCCI’00 (2000/09 - 2000/09)
Conference (Member of the Organising Committee)
2000 - 2000 IEEE/ACM Design, Automation and Test in Europe DATE (2000/03)
Conference (Member of the Scientific Committee)
1998 - 2000 IEEE International Symposium on Low Power Electronics and Design ISLPED (1998)
Conference (Member of the Scientific Committee)
1999 - 1999 General Vice-Chair, X IFIP International Conference on Very Large Scale Integration VLSI’99 (1999/12)
Conference (Member of the Organising Committee)

Evaluation committee

Activity description
Role 		Institution / Organization Funding entity
2019/09 - Current A3ES Academic Program Evaluation
Evaluator
2018 - Current FCT PhD Scholarships Selection Committee
Member
 Fundação para a Ciência e a Tecnologia, Portugal
2016/06 - Current Panel H2020 call ICT1-2016: Smart Cyber-Physical Systems
Evaluator
 European Commission Seventh Framework Programme for Research and Technological Development IDEAS The European Research Council, Belgium
2010 - Current PhD scholarships call
Evaluator
 Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2000 - Current Fulbrights scholarship applications evaluator
Specialist
 Fundação Luso-Americana, Portugal

Journal scientific committee

Journal title (ISSN) Publisher
2009 - 2017 VLSI Design (1563-5171) Hindawi Limited
Distinctions

Award

2021 Outstanding Paper Award
2015 Best paper award
13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC), China
2013 Best Paper Award
International SPIN Symposium on Model Checking of Software, United States
2002 Best paper award
1996 Best paper award for IEEE Transactions on VLSI Systems 1994/1995
IEEE, United States

Title

2010 Senior Member
IEEE, United States

Other distinction

1992 Fulbright Scholarship