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For the last few years, Aleksandar Ilic focused his research on the field of computer architectures, namely modern multi-core embedded/general-purpose processors (CPUs) and programmable accelerators, such as graphics processing units (GPUs). He is an Associate Professor with the Department of Electrical and Computer Engineering (DEEC) of Instituto Superior Técnico (IST), Universidade de Lisboa and he is currently developing his research work at INESC-ID Lisboa (Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa), Portugal. During the PhD, his research activities were mainly focused on investigating efficient strategies for task scheduling, dynamic load balancing, and runtime performance modeling in heterogeneous computing systems. This work considers not only single-node systems that combine devices of different architectures, but also multi-node clusters equipped with multi-core CPUs and several GPUs. For this, several applications from different scientific domains were considered, such as bioinformatics, video encoding, digital signal processing, linear algebra, and database applications. Aleksandar Ilic's research is also dedicated to designing and modeling of modern CPU architectures. More specifically, his research interests are focused on insightful modeling of modern multi-core architectures with complex memory hierarchies for performance, power consumption and energy-efficiency. As evidence of the impact of Aleksandar's research, in 2017, Intel Corporation fully integrated one of his research contributions (namely, the Cache-Aware Roofline Model) into their proprietary Intel Advisor tool, which is aimed at helping the end-costumers when analyzing and optimizing the execution of their applications. For this achievement, he received the HiPEAC Tech Transfer award in 2017. Furthermore, different approaches for the optimization and characterization of real-world applications are investigated, as well as novel scheduling strategies for efficient utilization of system and device resources. Based on these efforts, after finishing the PhD, Aleksandar Ilic has extended his main research lines to also include energy-aware task scheduling for modern heterogeneous embedded systems, tools for accurate application characterization and amending scheduling decisions at the operating system (OS) level, as well as automatic tuning of multiple data-parallel kernels for performance and energy-efficiency. In addition to the collaborative research with different INESC-ID scientific groups and action lines, Aleksandar is also involved in several international research and industry collaborations, such as with Intel Corporation (France and USA), AMD (US), Imagination Technologies/MIPS (UK), INRIA Bordeaux Sud-Ouest (France), Technische Universitat Berlin (Germany), University of Extremadura (Spain) etc. His research interests include high performance, power- and energy-efficient computing and micro-architectures for general purpose, embedded and specialized processors. In detail, his current research interests are aimed at developing efficient task scheduling and load balancing techniques for highly heterogeneous computing systems that combine different multi-core CPUs, GPUs and FPGA devices. Moreover, he is currently investigating efficient modeling, scheduling and monitoring approaches based on hardware monitoring events for different device architectures. -Program committee member several international conferences and workshops (including Cluster, Euro-Par, PPAM, HPCS, HeteroPar, SBAC-PAD,...); -Reviewer for research projects (Netherlands and Austrian Science Fund - FWF) and international conferences and journals (including IEEE TPDS, IEEE TComp, PARCO, PACT, ICS, IPDPS...); - Participation in the organization of EuroPar21, Cryptacus¿18 and ISPDC¿09 and several COST meetings and actions (IC0804/05); - Affiliate member of HiPEAC European Network of Excellence
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Identificação

Identificação pessoal

Nome completo
Aleksandar Ilic

Nomes de citação

  • Ilic, Aleksandar

Identificadores de autor

Ciência ID
ED15-73C2-57D1
ORCID iD
0000-0002-8594-3539
Google Scholar ID
HJks-BUAAAAJ

Websites

Domínios de atuação

  • Ciências da Engenharia e Tecnologias - Engenharia Eletrotécnica, Eletrónica e Informática - Hardware e Arquitetura de Computadores
  • Ciências Exatas - Ciências da Computação e da Informação
  • Ciências Exatas - Ciências da Computação e da Informação - Bioinformática

Idiomas

Idioma Conversação Leitura Escrita Compreensão Peer-review
Português Utilizador proficiente (C1) Utilizador proficiente (C1) Utilizador proficiente (C1) Utilizador proficiente (C1)
Sérvio Utilizador proficiente (C1) Utilizador proficiente (C1) Utilizador proficiente (C1) Utilizador proficiente (C1)
Inglês Utilizador proficiente (C1) Utilizador proficiente (C1) Utilizador proficiente (C1) Utilizador proficiente (C1)
Croata Utilizador proficiente (C1) Utilizador proficiente (C1) Utilizador proficiente (C1) Utilizador proficiente (C1)
Alemão Utilizador elementar (A1) Utilizador elementar (A1) Utilizador elementar (A1) Utilizador elementar (A1)
Formação
Grau Classificação
2014
Concluído
 Engenharia Electrotécnica e de Computadores (Doutoramento)
Especialização em Sem especialidade
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Heterogeneous Systems: Load Balancing and Performance Modeling" (TESE/DISSERTAÇÃO)
 Aprovado com Muito Bom com Distinção
2007
Concluído
 Electrical and Computer Engineering (Mestrado)
Univerzitet u Nisu Elektronski fakultet, Sérvia
"Architecture of a Processor with Hardware Speculation" (TESE/DISSERTAÇÃO)
 9.31/10
Percurso profissional

Ciência

Categoria Profissional
Instituição de acolhimento 		Empregador
2008/01/12 - Atual Investigador (Investigação) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2017/02/15 - 2017/07/15 Investigador visitante (Investigação) Inria Centre de recherche Bordeaux Sud-Ouest, França
2012/01/09 - 2012/01/29 Investigador visitante (Investigação) University College Dublin, Irlanda
2010/05/03 - 2010/05/18 Investigador visitante (Investigação) Inria Centre de recherche Bordeaux Sud-Ouest, França
2010/03/15 - 2010/04/11 Investigador visitante (Investigação) Universitat Jaume I, Espanha
2010/02/10 - 2010/02/24 Investigador visitante (Investigação) University College Dublin, Irlanda

Docência no Ensino Superior

Categoria Profissional
Instituição de acolhimento 		Empregador
2023/12/31 - Atual Professor Associado (Docente Universitário) Universidade de Lisboa Instituto Superior Técnico, Portugal
2014 - 2023 Professor Auxiliar (Docente Universitário) Universidade de Lisboa, Portugal
2015/11/10 - 2015/12/10 Professor Visitante (Docente Ensino Superior Politécnico) École Normale Supérieure Paris-Saclay, França
Projetos

Projeto

Designação Financiadores
2012 - Atual HiPEAC: European Network of Excellence on High Performance and Embedded Architecture and Compilation
687698
Outra
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Em curso
2023/03/10 - 2026/03/09 Compilação e Adaptação de Hardware para a Unificação da Computação Especializada e de Uso Geral
2022.06780.PTDC
10.54499/2022.06780.PTDC
Instituto de Telecomunicações Lisboa, Portugal

Instituto de Engenharia de Sistemas e Computadores Tecnologia e Ciência, Portugal

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Fundação para a Ciência e a Tecnologia
Em curso
2022/01/01 - 2025/12/31 Scaling extreme analYtics with Cross-architecture acceLeration based on OPen Standards¿
Grant agreement ID: 101092877
Co-Investigador Responsável (Co-IR)
Em curso
2021/04/01 - 2024/03/31 SparCity: An Optimization and Co-design Framework for Sparse Computation
956213
10.3030/956213
Co-Investigador Responsável (Co-IR)
European Commission
Concluído
2018/12/01 - 2021/12/31 SGA1 (Specific Grant Agreement 1) OF THE EUROPEAN PROCESSOR INITIATIVE (EPI)
826647
10.3030/826647
Team Member
European Commission
Concluído
2018/06/01 - 2021/12/31 Processamento de Elevado Desempenho e Energeticamente Eficiente para Aplicações de Bioinformática nos Sistemas Heterogéneos Emergentes
PTDC/CCI-COM/31901/2017
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Em curso
2014/04 - 2017/03 EMC2: Embedded Multi-core Systems for Mixed Criticality Applications in Dynamic and Changeable Real-Time Environments
ARTEMIS/0003/2013
Investigador
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Concluído
2013/05/01 - 2015/12/31 Transpondo os Limites do Processamento Paralelo em Sistemas Computacionais Heterogéneos
PTDC/EEI-ELC/3152/2012
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluído
2012/03/01 - 2015/08/31 THREadS: Framework para Sistemas Multi-Tarefa com Reconfiguração Transparente de Hardware
PTDC/EEA-ELC/117329/2010
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluído
2010 - 2013 KNOWTS: National Platform for Knowledge Triangle in Serbia
158881-TEMPUS-1-2009-1-RS-TEMPUS-JPHES
Outra
Concluído

Outro

Designação Financiadores
2018/07 - Atual IntelCARM: Boosting the roofline-based optimization guidance and performance modeling for modern CPU systems
IntelCARM
Investigador responsável
Intel Corporation
Em curso
Produções

Publicações

Artigo em conferência
  1. James D. Trotter; Sinan Ekmekçibasi; Johannes Langguth; Tugba Torun; Emre Düzakin; Aleksandar Ilic; Didem Unat. "Bringing Order to Sparsity: A Sparse Matrix Reordering Study on Multicore CPUs". 2023.
    10.1145/3581784.3607046
  2. Miguel Graca; Diogo Marques; Sergio Santander-Jiménez; Leonel Sousa; Aleksandar Ilic. "Interpreting High Order Epistasis Using Sparse Transformers". 2023.
    10.1145/3580252.3586982
  3. Nobre, Ricardo; Ilic, Aleksandar; Santander-Jiménez, Sergio; Sousa, Leonel. "Tensor-Accelerated Fourth-Order Epistasis Detection on GPUs". Trabalho apresentado em 51th International Conference on Parallel Processing (ICPP) [Ranked "A" in CORE2021], (Virtual) Bordeaux, 2022.
    10.1145/3545008.3545066
  4. Diogo Marques; Rafael Campos; Sergio Santander-Jiménez; Zakhar A. Matveev; Leonel Augusto Pires Seabra de Sousa; Aleksandar Ilic. "Unlocking Personalized Healthcare on Modern CPUs/GPUs: Three-way Gene Interaction Study". Trabalho apresentado em International Parallel & Distributed Processing Symposium (IPDPS 2022), 2022.
    Aceite para publicação • 10.48550/ARXIV.2201.10956
  5. Rafael Campos; Diogo Marques; Sergio Santander-Jimenez; Leonel Augusto Pires Seabra de Sousa; Aleksandar Ilic. "Epistasis Detection with DPC++ and OpenCL for Intel CPU and GPU". Trabalho apresentado em Simpósio de Informática, Computação Paralela, Distribuída e de Larga Escala (CPLDA/InForum’21), 2021.
  6. Nobre, Ricardo; Aleksandar Ilic; Sergio Santander-Jimenez; Leonel Augusto Pires Seabra de Sousa. "Fourth-Order Exhaustive Epistasis Detection for the xPU Era". 2021.
    10.1145/3472456.3472509
  7. Ribeiro, G.; Neves, N.; Santander-Jimenez, S.; Ilic, A.. "HEDAcc: FPGA-based Accelerator for High-order Epistasis Detection". 2021.
    10.1109/FCCM51124.2021.00022
  8. Campos, Rafael; Marques, Diogo; Santander-Jiménez, Sergio; Sousa, Leonel; Ilic, Aleksandar. "Heterogeneous CPU+iGPU Processing for Efficient Epistasis Detection". 2020.
    10.1007/978-3-030-57675-2_38
  9. Nobre, Ricardo; Santander-Jiménez, Sergio; Sousa, Leonel; Ilic, Aleksandar. "Accelerating 3-Way Epistasis Detection with CPU+GPU Processing". Trabalho apresentado em International Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP, collocated with IPDPS'20), 2020.
    10.1007/978-3-030-63171-0_6
  10. Freitas, H.R.A.; Mendes, C.L.; Ilic, A.. "Performance Optimization and Scalability Analysis of the MGB Hydrological Model". 2020.
    10.1109/HiPC50609.2020.00017
  11. Nobre, R.; Ilic, A.; Santander-Jimenez, S.; Sousa, L.. "Exploring the Binary Precision Capabilities of Tensor Cores for Epistasis Detection". 2020.
    10.1109/IPDPS47924.2020.00043
  12. Castro, Daniel; Romano, Paolo; Ilic, Aleksandar; Khan, Amin M.. "HeTM: Transactional Memory for Heterogeneous Systems". 2019.
    10.1109/pact.2019.00026
  13. Vieira, Alexandre; Pratas, Frederico; Sousa, Leonel; Ilic, Aleksandar. "Accelerating CNN computation". 2018.
    10.1145/3295816.3295820
  14. Guerreiro, Joao; Ilic, Aleksandar; Roma, Nuno; Tomas, Pedro. "GPGPU Power Modeling for Multi-domain Voltage-Frequency Scaling". 2018.
    10.1109/hpca.2018.00072
  15. Serrano, E.; Ilic, A.; Sousa, L.; Garcia-Blas, J.; Carretero, J.. "Cache-Aware Roofline Model and Medical Image Processing Optimizations in GPUs". Trabalho apresentado em ISC High Performance 2018: High Performance Computing, Workshop, 2018.
    10.1007/978-3-030-02465-9_36
  16. Denoyelle, N.; Goglin, B.; Ilic, A.; Jeannot, E.; Sousa, L.. "Modeling large compute nodes with heterogeneous memories with cache-aware roofline model". Trabalho apresentado em International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems, 2017.
    10.1007/978-3-319-72971-8_5
  17. David Pereira; Aleksandar Ilic; Leonel Sousa. "On Boosting Energy-Efficiency of Heterogeneous Embedded Systems via Game Theory". 2017.
    10.1145/3029580.3029584
  18. Marques, D.; Duarte, H.; Sousa, L.; Ilic, A.. "Analyzing performance of multi-cores and applications with cache-aware roofline model". 2017.
    10.1109/HPCS.2017.158
  19. Wang, B.; Alvarez-Mesa, M.; Chi, C.C.; Juurlink, B.; De Souza, D.F.; Ilic, A.; Roma, N.; et al. "Efficient HEVC decoder for heterogeneous CPU with GPU systems". 2017.
    10.1109/MMSP.2016.7813353
  20. Marques, D.; Duarte, H.; Ilic, A.; Sousa, L.; Belenov, R.; Thierry, P.; Matveev, Z.A.. "Performance analysis with cache-aware roofline model in intel advisor". 2017.
    10.1109/HPCS.2017.150
  21. Lopes, A.; Pratas, F.; Sousa, L.; Ilic, A.. "Exploring GPU performance, power and energy-efficiency bounds with Cache-Aware Roofline Modeling". 2017.
    10.1109/ISPASS.2017.7975297
  22. De Souza, D.F.; Ilic, A.; Roma, N.; Sousa, L.; Diego F. de Souza; Aleksandar Ilic; Nuno Roma; Leonel Sousa. "GPU acceleration of the HEVC decoder inter prediction module". 2016.
    10.1109/GlobalSIP.2015.7418397
  23. Diego F. de Souza; Aleksandar Ilic; Nuno Roma; Leonel Sousa; De Souza, D.F.; Ilic, A.; Roma, N.; Sousa, L.. "HEVC in-loop filters GPU parallelization in embedded systems". 2015.
    10.1109/samos.2015.7363667
  24. Diego de Souza, Aleksandar Ilic, Nuno Roma and Leonel Sousa. "Towards GPU HEVC Intra Decoding: Seizing Fine-Grain Parallelism". 2015.
    10.1109/ICME.2015.7177515
  25. João Guerreiro, Aleksandar Ilic, Nuno Roma and Pedro Tomás. "Multi-Kernel Auto-Tuning on GPUs: Performance and Energy-Aware Optimization". 2015.
    10.1109/PDP.2015.44
  26. Gaspar, F.; Tanica, L.; Tomas, P.; Ilic, A.; Sousa, L.. "Attaining performance fairness in big.LITTLE systems". 2015.
  27. Francisco Gaspar; Aleksandar Ilic; Pedro Tomas; Leonel Sousa. "Performance-Aware Task Management and Frequency Scaling in Embedded Systems". 2014.
    10.1109/sbac-pad.2014.14
  28. Momcilovic, Svetislav; Ilic, Aleksandar; Roma, Nuno; Sousa, Leonel. "Collaborative inter-prediction on CPU+GPU systems". 2014.
    10.1109/icip.2014.7025245
  29. Aleksandar Ilic; Svetislav Momcilovic; Nuno Roma; Leonel Sousa; Ilic, A.; Momcilovic, S.; Roma, N.; Sousa, L.. "FEVES: Framework for Efficient Parallel Video Encoding on Heterogeneous Systems". 2014.
    10.1109/icpp.2014.11
  30. Taniça, L.; Ilic, A.; Tomás, P.; Sousa, L.. "Schedmon: A performance and energy monitoring tool for modern multi-cores". Trabalho apresentado em International Workshop on Multi/Many-Core Computing Systems (MuCoCoS/Euro-Par 2014), 2014.
    Publicado
  31. Aleksandar Ilic; Leonel Sousa; Ilic, A.; Sousa, L.. "Simultaneous Multi-Level Divisible Load Balancing for Heterogeneous Desktop Systems". 2012.
    10.1109/ispa.2012.101
  32. Aleksandar Ilic; Leonel Sousa. "On Realistic Divisible Load Scheduling in Highly Heterogeneous Distributed Systems". 2012.
    10.1109/pdp.2012.56
  33. Ilic, A.; Sousa, L.. "Scheduling divisible loads on heterogeneous desktop systems with limited memory". Trabalho apresentado em International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar/Euro-Par 2011), 2011.
    Publicado • 10.1007/978-3-642-29737-3-54
  34. Aleksandar Ilic; Leonel Sousa; Ilic, A.; Sousa, L.. "Collaborative execution environment for heterogeneous parallel systems". 2010.
    10.1109/ipdpsw.2010.5470835
  35. Aleksandar Ilic; Frederico Pratas; Leonel Sousa. "Distributed Web-based Platform for Computer Architecture Simulation". 2008.
    10.1109/ispdc.2008.39
Artigo em revista
  1. Aleksandar Ilic; Leonel Sousa. "Special issue: 20th international workshop on algorithms, models and tools for parallel computing on heterogeneous platforms (HeteroPar'22)". Concurrency and Computation: Practice and Experience (2023): https://doi.org/10.1002/cpe.7915.
    10.1002/cpe.7915
  2. Luís M.S. Russo; Daniel Castro; Aleksandar Ilic; Paolo Romano; Ana D. Correia. "Stochastic simulated annealing for directed feedback vertex set". Applied Soft Computing (2022): https://doi.org/10.1016/j.asoc.2022.109607.
    10.1016/j.asoc.2022.109607
  3. Freitas, Henrique R.A.; Mendes, Celso L.; Ilic, Aleksandar. "Performance optimization of the MGB hydrological model for multi-core and GPU architectures". Environmental Modelling & Software 148 (2022): 105271. http://dx.doi.org/10.1016/j.envsoft.2021.105271.
    10.1016/j.envsoft.2021.105271
  4. Ricardo Nobre; Aleksandar Ilic; Sergio Santander-Jimenez; Leonel Sousa. "Retargeting Tensor Accelerators for Epistasis Detection". IEEE Transactions on Parallel and Distributed Systems 32 9 (2021): 2160-2174. https://doi.org/10.1109/TPDS.2021.3060322.
    10.1109/TPDS.2021.3060322
  5. Diogo Marques; Aleksandar Ilic; Leonel Augusto Pires Seabra de Sousa. "Mansard Roofline Model: Reinforcing the Accuracy of the Roofs". ACM Transactions on Modeling and Performance Evaluation of Computing Systems 6 2 (2021): 1-23. http://dx.doi.org/10.1145/3475866.
    10.1145/3475866
  6. Diogo Marques; Aleksandar Ilic; Zakhar A. Matveev; Leonel Sousa. "Application-driven Cache-Aware Roofline Model". Future Generation Computer Systems 107 (2020): 257-273. https://doi.org/10.1016%2Fj.future.2020.01.044.
    10.1016/j.future.2020.01.044
  7. Gonçalves, Francisco; Santander-Jiménez, Sergio; Sousa, Leonel; Granado-Criado, José M.; Ilic, Aleksandar. "Parallel evolutionary computation for multiobjective gene interaction analysis". Journal of Computational Science 40 (2020): 101068. http://dx.doi.org/10.1016/j.jocs.2019.101068.
    10.1016/j.jocs.2019.101068
  8. Joao Guerreiro; Aleksandar Ilic; Nuno Roma; Pedro Tomas. "Modeling and Decoupling the GPU Power Consumption for Cross-Domain DVFS". IEEE Transactions on Parallel and Distributed Systems 30 11 (2019): 2494-2506. https://doi.org/10.1109/TPDS.2019.2917181.
    10.1109/TPDS.2019.2917181
  9. Lopes, Paulo A.C.; Yadav, Satyendra Singh; Ilic, Aleksandar; Patra, Sarat Kumar. "Fast block distributed CUDA implementation of the Hungarian algorithm". Journal of Parallel and Distributed Computing 130 (2019): 50-62. http://dx.doi.org/10.1016/j.jpdc.2019.03.014.
    10.1016/j.jpdc.2019.03.014
  10. Nicolas Denoyelle; Brice Goglin; Aleksandar Ilic; Emmanuel Jeannot; Leonel Sousa. "Modeling Non-Uniform Memory Access on Large Compute Nodes with the Cache-Aware Roofline Model". IEEE Transactions on Parallel and Distributed Systems 30 6 (2019): 1374-1389. https://doi.org/10.1109/TPDS.2018.2883056.
    10.1109/TPDS.2018.2883056
  11. Guerreiro, João; Ilic, Aleksandar; Roma, Nuno; Tomás, Pedro. "DVFS-aware application classification to improve GPGPUs energy efficiency". Parallel Computing 83 (2019): 93-117. http://dx.doi.org/10.1016/j.parco.2018.02.001.
    10.1016/j.parco.2018.02.001
  12. Joao Guerreiro; Aleksandar Ilic; Nuno Roma; Pedro Tomas. "GPU Static Modeling Using PTX and Deep Structured Learning". IEEE Access 7 (2019): 159150-159161. https://doi.org/10.1109/ACCESS.2019.2951218.
    10.1109/ACCESS.2019.2951218
  13. Yadav, Satyendra Singh; Lopes, Paulo Alexandre Crisóstomo; Ilic, Aleksandar; Patra, Sarat Kumar. "Hungarian algorithm for subcarrier assignment problem using GPU and CUDA". International Journal of Communication Systems 32 4 (2018): e3884. http://dx.doi.org/10.1002/dac.3884.
    10.1002/dac.3884
  14. Wang, Biao; de Souza, Diego Felix; Alvarez-Mesa, Mauricio; Chi, Chi Ching; Juurlink, Ben; Ilic, Aleksandar; Roma, Nuno; Sousa, Leonel. "Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU". Signal Processing: Image Communication 62 (2018): 93-105. http://dx.doi.org/10.1016/j.image.2017.12.009.
    10.1016/j.image.2017.12.009
  15. Krzysztof Rojek; Aleksandar Ilic; Roman Wyrzykowski; Leonel Sousa. "Energy-aware mechanism for stencil-based MPDATA algorithm with constraints". Concurrency and Computation: Practice and Experience 29 8 (2017): e4016-e4016. https://doi.org/10.1002%2Fcpe.4016.
    10.1002/cpe.4016
  16. Sergio Santander-Jiménez; Aleksandar Ilic; Leonel Sousa; Miguel A. Vega-Rodríguez. "Accelerating the phylogenetic parsimony function on heterogeneous systems". Concurrency and Computation: Practice and Experience 29 8 (2017): e4046-e4046. https://doi.org/10.1002%2Fcpe.4046.
    10.1002/cpe.4046
  17. Diego F. de Souza; Aleksandar Ilic; Nuno Roma; Leonel Sousa; De Souza, D.F.; Ilic, A.; Roma, N.; Sousa, L.. "GHEVC: An Efficient HEVC Decoder for Graphics Processing Units". IEEE Transactions on Multimedia 19 3 (2017): 459-474. https://doi.org/10.1109%2Ftmm.2016.2625261.
    10.1109/tmm.2016.2625261
  18. Aleksandar Ilic; Frederico Pratas; Leonel Sousa. "Beyond the Roofline: Cache-Aware Power and Energy-Efficiency Modeling for Multi-Cores". IEEE Transactions on Computers 66 1 (2017): 52-58. https://doi.org/10.1109%2Ftc.2016.2582151.
    10.1109/tc.2016.2582151
  19. Biao Wang; Diego F. de Souza; Mauricio Alvarez-Mesa; Chi Ching Chi; Ben Juurlink; Aleksandar Ilic; Nuno Roma; Leonel Sousa. "GPU Parallelization of HEVC In-Loop Filters". International Journal of Parallel Programming (2017): https://doi.org/10.1007%2Fs10766-017-0488-z.
    10.1007/s10766-017-0488-z
  20. Diego de Souza, Aleksandar Ilic, Nuno Roma and Leonel Sousa. "GPU-assisted HEVC Intra Decoder". Journal of Real-Time Image Processing (2016):
    10.1007/s11554-015-0519-1
  21. Francisco Gaspar; Luis Taniça; Pedro Tomás; Aleksandar Ilic; Leonel Sousa. "A Framework for Application-Guided Task Management on Heterogeneous Embedded Systems". ACM Transactions on Architecture and Code Optimization 12 4 (2016): 1-25. https://doi.org/10.1145%2F2835177.
    10.1145/2835177
  22. Aleksandar Ilic, Svetislav Momcilovic, Nuno Roma and Leonel Sousa. "Adaptive Scheduling Framework for Real-Time Video Encoding on Heterogeneous Systems". IEEE Transactions on Circuits and Systems for Video Technology (2015):
    10.1109/TCSVT.2015.2402893
  23. Ilic, Aleksandar; Pratas, Frederico; Sousa, Leonel. "Cache-aware Roofline model: Upgrading the loft". Ieee Computer Architecture Letters 13 1 (2014): 21-24. http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=ORCID&SrcApp=OrcidOrg&DestLinkType=FullRecord&DestApp=WOS_CPL&KeyUT=WOS:000344987900006&KeyUID=WOS:000344987900006.
    10.1109/L-CA.2013.6
  24. Momcilovic, Svetislav; Ilic, Aleksandar; Roma, Nuno; Sousa, Leonel. "Dynamic Load Balancing for Real-Time Video Encoding on Heterogeneous CPU+GPU Systems". IEEE Transactions on Multimedia 16 1 (2014): 108-121. http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=ORCID&SrcApp=OrcidOrg&DestLinkType=FullRecord&DestApp=WOS_CPL&KeyUT=WOS:000328948100010&KeyUID=WOS:000328948100010.
    10.1109/TMM.2013.2284892
  25. Clarke, David; Ilic, Aleksandar; Lastovetsky, Alexey; Sousa, Leonel; Kaklamanis, C; Papatheodorou, T; Spirakis, PG. "Hierarchical Partitioning Algorithm for Scientific Computing on Highly Heterogeneous CPU plus GPU Clusters". Euro-Par 2012 Parallel Processing 7484 (2012): 489-501. http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=ORCID&SrcApp=OrcidOrg&DestLinkType=FullRecord&DestApp=WOS_CPL&KeyUT=WOS:000341235300049&KeyUID=WOS:000341235300049.
    10.1007/978-3-642-32820-6_49
  26. Aleksandar Ilic; Leonel Sousa. "CHPS: An Environment for Collaborative Execution on Heterogeneous Desktop Systems". International Journal of Networking and Computing 1 1 (2011): 96-113. https://doi.org/10.15803%2Fijnc.1.1_96.
    10.15803/ijnc.1.1_96
Capítulo de livro
  1. Alexandre Rodrigues; Leonel Sousa; Aleksandar Ilic. "A Performance Modelling-Driven Approach to Hardware Resource Scaling". 2024.
    10.1007/978-3-031-48803-0_15
  2. Alexandre Rodrigues; Leonel Sousa; Aleksandar Ilic. "Performance Modelling-Driven Optimization of RISC-V Hardware for Efficient SpMV". 2023.
    10.1007/978-3-031-40843-4_36
  3. Guerreiro, João; Ilic, Aleksandar; Roma, Nuno; Tomás, Pedro. "Performance and Power-Aware Classification for Frequency Scaling of GPGPU Applications". In Euro-Par 2016: Parallel Processing Workshops, 134-146. Springer International Publishing, 2017.
    10.1007/978-3-319-58943-5_11
  4. Colaco, Joao; Matoga, Adrian; Ilic, Aleksandar; Roma, Nuno; Tomas, Pedro; Chaves, Ricardo; Wyrzykowski, R; et al. "Transparent Application Acceleration by Intelligent Scheduling of Shared Library Calls on Heterogeneous Systems". 693-703. 2014.
    10.1007/978-3-642-55224-3_65
  5. Ilic, Aleksandar; Sousa, Leonel; Ilic, A.; Sousa, L.. "Efficient Multilevel Load Balancing on Heterogeneous CPU + GPU Systems". editado por Jeannot, Emmanuel; Žilinskas, Julius, 261-282. 2014.
    10.1002/9781118711897.ch14
  6. Antao, Diogo; Tanica, Luis; Ilic, Aleksandar; Pratas, Frederico; Tomas, Pedro; Sousa, Leonel; Wyrzykowski, R; et al. "Monitoring Performance and Power for Application Characterization with the Cache-Aware Roofline Model". 747-760. 2014.
    10.1007/978-3-642-55224-3_70
  7. Clarke, David; Ilic, Aleksandar; Lastovetsky, Alexey; Rychkov, Vladimir; Sousa, Leonel; Zhong, Ziming; Clarke, D.; et al. "Design and Optimization of Scientific Applications for Highly Heterogeneous and Hierarchical HPC Platforms Using Functional Computation Performance Models". editado por Jeannot, Emmanuel; Žilinskas, Julius, 235-260. 2014.
    10.1002/9781118711897.ch13
  8. Ilic, Aleksandar; Pratas, Frederico; Trancoso, Pedro; Sousa, Leonel. "High-Performance Computing on Heterogeneous Systems: Database Queries on CPU and GPU". editado por Foster, Ian; Gentzsch, Wolfgang; Grandinetti, Lucio; Joubert, Gerhard R., 202-222. 2011.
    10.3233/978-1-60750-803-8-202
Atividades

Apresentação oral de trabalho

Título da apresentação Nome do evento
Anfitrião (Local do evento)
2021/11 Performance Tuning with the Roofline Model on GPUs and CPUs International Conference for High Performance Computing, Networking, Storage, and Analysis (SC’21)
2021/11 Application optimization with Cache-aware Roofline Model and Intel oneAPI tools Intel oneAPI Developer Summit at SC’21
Intel
2021/06 Cache-aware Roofline Model: Application optimization with Intel oneAPI tools Intel oneAPI Developer Summit at ISC High Performance (ISC)
Intel Corporation
2021/04 Application optimization with Cache-aware Roofline Model and Intel oneAPI tools Intel oneAPI Developer Summit at International Workshop on OpenCL (IWOCL) and SYCL (SYCLcon)
Intel
2020/11 Performance Tuning with the Roofline Model on GPUs and CPUs International Conference for High Performance Computing, Networking, Storage and Analysis (SC)
2020/11 Rooflining Bioinformatics: Boosting Epistasis Detection with Cache-aware Roofline Model Intel oneAPI Developer Summit
2020/10 Cache-Aware Roofline Model: Performance, Power and Energy-Efficiency Intel eXtreme Performance User Group conference (IXPUG)
Intel Corporation
2019 Performance Optimization of Scientific Codes with the Roofline Model ISC High Performance 2019, Tutorial
(Alemanha)
2019 Performance Tuning with the Roofline Model on GPUs and CPUs nternational Conference for High Performance Computing, Networking, Storage and Analysis (SC), Tutorial,
(Estados Unidos)
2018/11 Cache-aware Roofline Model: Performance, Power and Energy-Efficiency Modeling of Parallel Processors International Conference on Parallel Architectures and Compilation Techniques (PACT'18), Tutorial
(Chipre)
2018/11 Performance Tuning of Scientific Codes with the Roofline Model International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Tutorial
(Estados Unidos)
2018 Cache-aware Roofline Model: Performance, Power and Energy-Efficiency Modeling of Parallel Processors International Symposium on Performance Analysis of Systems and Software (ISPASS), Tutorial
2018 A Practical Approach to Application Performance tuning with the Roofline Model ISC High Performance 2018, Tutorial
(Alemanha)
2018 Performance Tuning with Cache-aware Roofline Model in Intel® Advisor Intel Speakership at SC'18, Tutorial
(Estados Unidos)
2017 Performance Tuning of Scientific Codes with the Roofline Model International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Tutorial
(Estados Unidos)
2017 Tuning for the Intel® Xeon® Scalable Processor (Code Named Skylake) Intel® HPC Developer Conference, Tutorial
(Estados Unidos)
2017 Cache-aware Roofline Model: Performance, Power and Energy-Efficiency Modeling of Multi-Cores High Performance and Embedded Architecture and Compilation Conference (HiPEAC), Tutorial
(Suécia)
2017 Cache-aware Roofline Model: Performance, Power and Energy-Efficiency Modeling of Multi-Cores NESUS Winter School and PhD Symposium, Tutorial
(Itália)
2017 Cache-aware Roofline Model: Performance, Power and Energy-Efficiency Modeling of Parallel Processors International Conference on High Performance Computing & Simulation (HPCS), Tutorial
(Itália)
2017 Analyzing Performance of Multi-cores and Applications with Cache-aware Roofline Model Special Session on High Performance Computing for Application Benchmarking and Optimization (HPBench'17), International Conference on High Performance Computing & Simulation (HPCS'17)
(Itália)
2015 Cache-Aware Roofline Model: Performance, Power and Energy-Efficiency Avancées sur les modèles de performance pour les nouvelles architectures HPC (Seminaire Exceptionnel)
CMLA, ENS Cachan, Université Paris-Saclay (França)

Orientação

Título / Tema
Papel desempenhado 		Curso (Tipo)
Instituição / Organização
2023 - 2023 Deep Learning based Side Channel Attacks on Intel CPU
Orientador
 Engenharia Electrotécnica Militar (Mestrado)
Academia Militar, Portugal
2023 - 2023 BAIopSY: Bioinformatics Acceleration Framework for AI-Based Heterogeneous Systems
Orientador
 Engenharia Electrotécnica e de Computadores (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2021 - 2021 PhyloMissForest: a framework to construct phylogenetic trees with missing data
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2021 - 2021 Hacking the systems from within
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020 - 2021 PhyloMissForest: a framework to construct phylogenetic trees with missing data
Orientador
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020 - 2021 Hacking the systems from within
Orientador
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020 - 2021 FPGA-Based Accelerator for High-Order Epistasis Detection
Orientador
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020 - 2020 Hacking the systems from within
Orientador
 Engenharia Informática e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020 - 2020 Single and Multi-Objective Epistasis Scoring: A Matter of Frequency
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2019 - 2020 Hacking the systems from within
Orientador
Universidade de Lisboa Instituto Superior Técnico, Portugal
2019 - 2020 Single and Multi-Objective Epistasis Scoring: A Matter of Frequency
Orientador
Universidade de Lisboa Instituto Superior Técnico, Portugal
2019 - 2020 Exploring processor frontend capabilities via micro-benchmarking
Orientador
Universidade de Lisboa Instituto Superior Técnico, Portugal
2019 - 2019 Exploring the Efficiency of Bioinformatics Applications with CPUs, Integrated GPUs and Processing-in-Memory
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018 - 2019 Exploring the Efficiency of Bioinformatics Applications with CPUs, Integrated GPUs and Processing-in-Memory
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018 - 2019 Machine Learning and Computational Intelligence for High-Order Epistasis Detection
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018 - 2019 Boosting the performance of multi-objective epistasis detection
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018 - 2019 TLS for Internet of Things
Orientador
 Engenharia Informática e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018 - 2018 Performance Analysis of Intel Gen9.5 Integrated GPU Architecture
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018 - 2018 High Performance and Energy-efficient Computing for Highly Heterogeneous Systems
Orientador
 Engenharia Electrotécnica e de Computadores (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 - 2017 GipherFS - A GPU Accelerated Ciphered File System
Orientador
 Engenharia Informática e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 - 2017 Secure external memory on embedded devices
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 - 2017 Performance and Energy-Efficiency Modelling for Multi-Core Processors
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 - 2017 Parallel Ultra Low Power Embedded System
Coorientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016 - 2017 Exploring GPU performance, power and energy-efficiency bounds with Cache-aware Roofline Modeling
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016 - 2016 Boosting Energy-Efficiency of Heterogeneous Embedded Systems via Game Theory
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016 - 2016 Transactional Memory for heterogeneous CPU-GPU Systems
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2014 - 2014 Performance and energy-aware real-time scheduling for heterogeneous embedded systems
Coorientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2014 - 2014 KerMon: Framework for in-kernel performance and energy monitoring
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal

Organização de evento

Nome do evento
Tipo de evento (Tipo de participação) 		Instituição / Organização
2021 - 2021 International European Conference on Parallel and Distributed Computing (Euro-Par'21) (2021/08 - 2021/09)
2018/04 - 2018/04 Training School on Cryptanalysis of Ubiquitous Computing Systems (CRYPTACUS'18) (2018/04 - 2018/04)
Simpósio (Membro da Comissão Organizadora)
 Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Participação em evento

Descrição da atividade
Tipo de evento 		Nome do evento
Instituição / Organização
2019 - 2019 Cache-Aware Roofline Model: Uncovering micro-architecture upper-bounds
Conferência
 PADAL Workshop, Bordeaux, France
Inria Centre de recherche Bordeaux Sud-Ouest, França

Comissão de avaliação

Descrição da atividade
Tipo de assessoria 		Instituição / Organização Entidade financiadora
2014 - 2014 Evaluator of International Joint Research Project
Avaliador
 Fonds zur Förderung der wissenschaftlichen Forschung, Áustria

Membro de comissão

Descrição da atividade
Tipo de participação 		Instituição / Organização
2021 - 2021 IEEE Cluster Conference (CLUSTER'21)
Membro
2021 - 2021 Workshop em Sistemas Embebidos e de Tempo Real / INForum'21
Membro
2020 - 2020 International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar'20), EuroPar 2020
Membro
2020 - 2020 International Conference on High Performance Computing & Simulation (HPCS'20)
Membro
2020 - 2020 IEEE Cluster Conference (CLUSTER'20)
Membro
2019 - 2019 International Conference on Parallel Processing and Applied Mathematics (PPAM'19)
Membro
2019 - 2019 International Workshop on Data Locality (COLOC'19), EuroPar 2019
Membro
2019 - 2019 International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar'19), EuroPar 2019
Membro
2019 - 2019 Workshop em Sistemas Embebidos e de Tempo Real / INForum'19
Membro
2019 - 2019 International Conference on High Performance Computing & Simulation (HPCS'19)
Membro
2018 - 2018 Workshop em Sistemas Embebidos e de Tempo Real / INForum'18
Membro
2018 - 2018 International Conference on High Performance Computing & Simulation (HPCS'18)
Membro
2018 - 2018 International Workshop on Data Locality (COLOC'18), EuroPar 2018
Membro
2018 - 2018 International European Conference on Parallel and Distributed Computing (Euro-Par'18)
Membro
2017 - 2017 Workshop em Sistemas Embebidos e de Tempo Real / INForum'17
Membro
2017 - 2017 International Conference on High Performance Computing & Simulation (HPCS'17)
Membro
2017 - 2017 International Workshop on Data Locality (COLOC'17), EuroPar 2017
Membro
2017 - 2017 International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar'17), EuroPar 2017
Membro
2017 - 2017 International Conference on Parallel Processing and Applied Mathematics (PPAM'17)
Membro
2016 - 2016 Workshop em Sistemas Embebidos e de Tempo Real / INForum'16
Membro
2015 - 2015 Workshop em Sistemas Embebidos e de Tempo Real, INForum'15
Membro
2015 - 2015 International Conference on Parallel Processing and Applied Mathematics (PPAM'15)
Membro
2014 - 2014 International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'14)
Membro
Distinções

Prémio

2019 IST Outstanding Teaching Award
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 HiPEAC Tech Transfer Award
European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), Bélgica
2015 Best Young Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2000 Special Award for success in first year of study
Univerzitet u Nisu Elektronski fakultet, Sérvia

Título

2014 Awarded European PhD degree with Distinction (awarded to less than 20% of the PhDs at IST)
Universidade de Lisboa Instituto Superior Técnico, Portugal

Outra distinção

2020 Intel Software Innovator
Intel Corporation, Estados Unidos
2016 Cor Baayen Award Finalist
European Research Consortium for Informatics and Mathematics, França
2013 Ranked 2nd at the national level (Concurso para a atribuição de Bolsas Individuais de Pós-Doutoramento, area: Computer Science and Engineering)
Fundação para a Ciência e a Tecnologia, Portugal