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João M. P. Cardoso got his PhD degree in Electrical and Computer Engineering from the IST/UTL (Technical University of Lisbon), Lisbon, Portugal in 2001. He is a Full Professor at the Department of Informatics Engineering, Faculty of Engineering of the University of Porto, Porto, Portugal, and a senior researcher of INESC TEC. Before, he was with the IST/UTL (2006-2008), a senior researcher at INESC-ID (2001-2009), and with the University of Algarve (1993-2006). In 2001/2002, he worked for PACT XPP Technologies, Inc., Munich, Germany. He has been involved in the organization and served as Program Committee member for many international conferences. He was general Co-Chair of IEEE/IFIP EUC'2015 and IEEE CSE'2015, General Chair of IEEE ASAP'2023, FPL'2013, General Co-Chair of ARC'2014 and ARC'2006, Program Co-Chair of HEART'2019, ARCS'2016, DASIP'2014, and RAW'2010. He is co-author of two books (Elsevier and Springer), co-editor of two Springer Books and four Springer LNCS volumes. He has (co-)authored over 250 scientific publications (including journal/conference papers and patents) on subjects related to compilers, high-level synthesis, application-specific architectures, embedded computing, FPGAs, and reconfigurable computing. He has participated in a number of international research projects, e.g., as technical manager of the H2020 EU-funded project ANTAREX (2015-2018), co-scientific coordinator of the FP7 EU-funded project REFLECT (2010-2012), and as coordinator of various national funded projects. He is a senior member of IEEE, a member of IEEE Computer Society, and a senior member of ACM. His research interests include compiler techniques, domain-specific languages, reconfigurable computing, FPGAs, high-level synthesis. application-specific architectures, embedded and high-performance computing, and performance engineering.
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Identificação

Identificação pessoal

Nome completo
João Cardoso

Nomes de citação

  • Cardoso, João
  • João MP Cardoso

Identificadores de autor

Ciência ID
5C1C-8247-D614
ORCID iD
0000-0002-7353-1799
Google Scholar ID
https://scholar.google.com/citations?user=qGdlCzQAAAAJ&hl=pt-PT
Researcher Id
C-5552-2008
Scopus Author Id
9639597300

Endereços de correio eletrónico

  • jmpc@acm.org (Profissional)

Moradas

  • Faculdade de Engenharia da Universidade do Porto (FEUP), Departamento de Engenharia Informática, Rua Dr. Roberto Frias, 4200-465, Porto , Porto, Portugal (Profissional)

Websites

Domínios de atuação

  • Ciências Exatas - Ciências da Computação e da Informação - Ciências da Computação
  • Ciências da Engenharia e Tecnologias - Engenharia Eletrotécnica, Eletrónica e Informática
Formação
Grau Classificação
2015/09/15
Concluído
 Joao Cardoso (Título de Agregado)
Especialização em Informatics Engineering
Universidade do Porto Faculdade de Engenharia, Portugal
2001
Concluído
 Electrical and Computer Engineering (Doutoramento)
Especialização em Sem especialidade
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Compilação de Algoritmos em Java Tm para Sistemas Computacionais Reconfiguráveis com Exploração do Paralelismo ao Nível das Operações" (TESE/DISSERTAÇÃO)
1997/03/21
Concluído
 Electrical and Computer Engineering (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
1993/09/22
Concluído
 Electronics and Telecommunications Engineering (Licenciatura)
Universidade de Aveiro, Portugal
Percurso profissional

Ciência

Categoria Profissional
Instituição de acolhimento 		Empregador
2011/07/01 - Atual Investigador principal (carreira) (Investigação) Instituto de Engenharia de Sistemas e Computadores Tecnologia e Ciência Center for Research in Advanced Computing Systems, Portugal
1996 - 2009 Investigador (Investigação) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Docência no Ensino Superior

Categoria Profissional
Instituição de acolhimento 		Empregador
2016 - Atual Professor Catedrático (Docente Universitário) Universidade do Porto Faculdade de Engenharia, Portugal
2016 - 2018 Professor Catedrático (Docente Universitário) Universidade do Porto, Portugal
2013 - 2016 Professor Associado (Docente Universitário) Universidade do Porto Faculdade de Engenharia, Portugal
2013 - 2016 Professor Associado (Docente Universitário) Universidade do Porto Faculdade de Engenharia, Portugal
2006/04/04 - 2008/09/03 Professor Auxiliar (Docente Universitário) Universidade de Lisboa Instituto Superior Técnico, Portugal
2001/04/02 - 2006/02/22 Professor Auxiliar (Docente Universitário) Universidade do Algarve - Campus de Gambelas, Portugal
1997/03/21 - 2001/04/01 Assistente (Docente Universitário) Universidade do Algarve - Campus de Gambelas, Portugal
1993/12/15 - 1997/03/20 Assistente Estagiário (Docente Universitário) Universidade do Algarve - Campus de Gambelas, Portugal

Cargos e Funções

Categoria Profissional
Instituição de acolhimento 		Empregador
2017 - Atual Head of the Informatics Engineering Department Universidade do Porto Faculdade de Engenharia, Portugal
Universidade do Porto Faculdade de Engenharia, Portugal
2016 - 2018 Coordenação ou direção de centro de investigação, departamento ou equivalente Universidade do Porto, Portugal

Outros

Categoria Profissional
Instituição de acolhimento 		Empregador
2001/08 - 2002/08 Compiler Specialist XPP Technologies, Inc., Alemanha
Projetos

Bolsa

Designação Financiadores
2015/09 - 2018/08 AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems
grant.671623
 European Commission
2013/01 - 2015/06 BESTCASE-RL8-REALTIME: Languages and tools for critical real time systems
NORTE-01-0124-FEDER-000062
 Autoriadade de Gestão do Programa Operacional Regional do Norte
2010/01 - 2012/12 Rendering FPGAs to Multi-Core Embedded Computing
grant.248976
 European Commission
2004/01 - 2007/07 CHIADO: Compilation of High-Level Computationally Intensive Algorithms to Dynamically Reconfigurable COmputing Systems
Provided by PTCRIS: 48018
 Fundação para a Ciência e a Tecnologia, I.P.

Projeto

Designação Financiadores
2018/10/01 - 2021/09/30 Power Efficiency and Performance for Embedded and HPC Systems with Custom CGRAs
PTDC/EEI-HAC/30848/2017
Instituto de Engenharia de Sistemas e Computadores Tecnologia e Ciência, Portugal

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Fundação para a Ciência e a Tecnologia
Em curso
2016/06/01 - 2019/12/31 Middleware and Context Inference Techniques from Data-Streams for the Development of Context-Aware Services using Mobile Devices
PTDC/EEI-SCR/6945/2014
Instituto de Engenharia de Sistemas e Computadores, Portugal

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

MEO Serviços de Comunicações e Multimédia SA, Portugal
Fundação para a Ciência e a Tecnologia
Concluído
2012/04/01 - 2015/04/30 AutoSeer: Automated Test Oracles for Software Error Detection
PTDC/EIA-CCO/116796/2010
Universidade do Minho Centro ALGORITMI, Portugal

Universidade do Porto Faculdade de Engenharia, Portugal

Universidade do Minho, Portugal
Fundação para a Ciência e a Tecnologia
Concluído
2007/12/01 - 2011/11/30 AMADEUS: ASPECTS AND COMPILER OPTIMIZATIONS FOR MATLAB SYSTEM DEVELOPMENT
PTDC/EIA/70271/2006
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Universidade do Porto Faculdade de Engenharia, Portugal

Universidade Nova de Lisboa UNINOVA Instituto de Desenvolvimento de Novas Tecnologias, Portugal

Universidade do Minho, Portugal

Associação para a Inovação e Desenvolvimento da FCT, Portugal
Fundação para a Ciência e a Tecnologia
Concluído
2007/10/01 - 2011/03/31 COBAYA: CLOSING THE COMPILATION GAP BETWEEN ALGORITHMS AND COARSE-GRAINED RECONFIGURABLE ARRAY ARCHITECTURES
PTDC/EEA-ELC/70272/2006
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Universidade do Porto Faculdade de Engenharia, Portugal
Fundação para a Ciência e a Tecnologia
Concluído
Produções

Publicações

Artigo em conferência
  1. Pinto, P; Cardoso, JMP. "A methodology and framework for software memoization of functions". 2021.
    10.1145/3457388.3458668
  2. Campos, R; Cardoso, JMP. "On Data Parallelism Code Restructuring for HLS Targeting FPGAs". 2021.
    10.1109/ipdpsw52791.2021.00029
  3. Santos, T; Paulino, N; Bispo, J; Cardoso, JMP; Ferreira, JC. "On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators". 2021.
    10.1109/icfpt52863.2021.9609868
  4. Crarcia, KD; Carvalho, T; Mendes Moreira, J; Cardoso, JMP; de Carvalho, ACPLF. "A Study on Hyperparameter Configuration for Human Activity Recognition". 2020.
    10.1007/978-3-030-20055-8_5
  5. Paulino, N; Ferreira, JC; Bispo, J; Cardoso, JMP. "Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework". 2020.
    10.1109/fpl50879.2020.00072
  6. Santos, T; Cardoso, JMP. "Automatic Selection and Insertion of HLS Directives Via a Source-to-Source Compiler". 2020.
    10.1109/icfpt51103.2020.00039
  7. Afonso Canas Ferreira; João M. P. Cardoso. "Graph-Based Code Restructuring Targeting HLS for FPGAs". 2019.
    10.1007/978-3-030-17227-5_17
  8. Ricardo M. C. Magalhães; João M. P. Cardoso; João Mendes-Moreira. "Energy Efficient Smartphone-Based Users Activity Classification". 2019.
    10.1007/978-3-030-30244-3_18
  9. Paulo J. S. Ferreira; João M. P. Cardoso; João Mendes-Moreira. "Automatic Switching Between Video and Audio According to User’s Context". 2019.
    10.1007/978-3-030-30244-3_17
  10. Paulo J. S. Ferreira; Ricardo M. C. Magalhães; Kemilly Dearo Garcia; João M. P. Cardoso; João Mendes-Moreira. "An Efficient Scheme for Prototyping kNN in the Context of Real-Time Human Activity Recognition". 2019.
    10.1007/978-3-030-33607-3_52
  11. Silvano, C; Agosta, G; Bartolini, A; Beccari, AR; Benini, L; Besnard, L; Bispo, J; et al. "Supporting the Scale-up of High Performance Application to Pre-Exascale Systems: The ANTAREX Approach". 2019.
    10.1109/pdp.2019.00024
  12. Ferreira, A.C.; Cardoso, J.M.P.. "Unfolding and folding: A new approach for code restructuring targeting HLS for FPGAs". 2019.
  13. Ricardo Nobre; Luís Reis; João M. P. Cardoso. "Impact of Compiler Phase Ordering When Targeting GPUs". 2018.
    10.1007/978-3-319-75178-8_35
  14. Gadioli, D; Nobre, R; Pinto, P; Vitali, E; Ashouri, AH; Palermo, G; Cardoso, JMP; Silvano, C. "SOCRATES - A seamless online compiler and system runtime autotuning framework for energy-aware applications". 2018.
    10.23919/date.2018.8342183
  15. Carvalho, T; Cardoso, JMP. "An Approach Based on a DSL plus API for Programming Runtime Adaptivity and Autotuning Concerns". 2018.
    10.1145/3167132.3167263
  16. Arabnejad, H; Bispo, J; Barbosa, JG; Cardoso, JMP. "AutoPar-Clava: An Automatic Parallelization source-to-source tool for C code applications". 2018.
    10.1145/3183767.3183770
  17. Reis, L; Nobre, R; Cardoso, JMP. "Impact of Vectorization Over 16-bit Data-Types on GPUs". 2018.
    10.1145/3183767.3183777
  18. Nobre, R; Reis, L; Bispo, J; Carvalho, T; Cardoso, JMP; Cherubin, S; Agosta, G. "Aspect-Driven Mixed-Precision Tuning Targeting GPUs". 2018.
    10.1145/3183767.3183776
  19. Silvano, C; Palermo, G; Agosta, G; Ashouri, AH; Gadioli, D; Cherubin, S; Vitali, E; et al. "Autotuning and adaptivity in energy efficient HPC systems: the ANTAREX toolbox". 2018.
    10.1145/3203217.3205338
  20. Arabnejad, H; Bispo, J; Barbosa, JG; Cardoso, JMP. "An OpenMP based Parallelization Compiler for C Applications". 2018.
    10.1109/bdcloud.2018.00135
  21. Silvano, C; Agosta, G; Bartolini, A; Beccari, AR; Benini, L; Besnard, L; Bispo, J; et al. "ANTAREX: A DSL-Based Approach to Adaptively Optimizing and Enforcing Extra-Functional Properties in High Performance Computing". 2018.
    10.1109/DSD.2018.00105
  22. Nobre, R; Reis, L; Cardoso, JMP. "Fast Heuristic-Based GPU Compiler Sequence Specialization". 2018.
    10.1007/978-3-030-10549-5_39
  23. Khan, S; Khalid, F; Hasan, O; Cardoso, JMP. "Formal verification of a domain specific language for run-time adaptation". 2018.
    10.1109/syscon.2018.8369520
  24. Silvano, C.; Cardoso, J.M.P.; Fornaciari, W.; Huebner, M.. "Message from general and program co-chairs". 2018.
  25. Cardoso, J.M.P.; Casseau, E.; Langlois, P.; Juárez, E.. "Message from DASIP'2018 General and Program Chairs". 2018.
    10.1109/DASIP.2018.8597039
  26. Khan, S.; Khalid, F.; Hasan, O.; Cardoso, J.M.P.. "Formal verification of a domain specific language for run-time adaptation". 2018.
    10.1109/SYSCON.2018.8369520
  27. Reis, L; Bispo, J; Cardoso, JMP. "Compiler Techniques for Efficient MATLAB to OpenCL Code Generation". 2017.
    10.1145/3078155.3078186
  28. Golasowski, M; Bispo, J; Martinovic, J; Slaninova, K; Cardoso, JMP. "Expressing and Applying C plus plus Code Transformations for the HDF5 API Through a DSL". 2017.
    10.1007/978-3-319-59105-6_26
  29. Pinto, P; Carvalho, T; Bispo, J; Cardoso, JMP. "LARA as a language-independent aspect-oriented programming approach". 2017.
    10.1145/3019612.3019749
  30. Monteiro, MP; Marques, NC; Silva, B; Palma, B; Cardoso, J. "Toward a Token-Based Approach to Concern Detection in MATLAB Sources". 2017.
    10.1007/978-3-319-65340-2_47
  31. Silvano, C; Agosta, G; Barbosa, JG; Bartolini, A; Beccari, AR; Benini, L; Bispo, J; et al. "The ANTAREX tool flow for monitoring and autotuning energy efficient HPC systems". 2017.
    10.1109/samos.2017.8344645
  32. Reis, L; Bispo, J; Cardoso, JMP. "SSA-based MATLAB-to-C compilation and optimization". 2016.
    10.1145/2935323.2935330
  33. Silvano, C; Agosta, G; Bartolini, A; Beccari, AR; Benini, L; Bispo, J; Cmar, R; et al. "Autotuning and adaptivity approach for energy efficient Exascale HPC systems: The ANTAREX approach". 2016.
  34. Hannig, F; Cardoso, JMP; Pionteck, T; Fey, D; Preikschat, WS; Teich, J. "Architecture of computing systems – ARCS 2016: 29th international conference Nuremberg, Germany, April 4-7, 2016 Proceedings". 2016.
    10.1007/978-3-319-30695-7
  35. Silvano, C; Agosta, G; Cherubin, S; Gadioli, D; Palermo, G; Bartolini, A; Benini, L; et al. "The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems". 2016.
    10.1145/2903150.2903470
  36. Holanda, JoseArnaldoMascagnide; Cardoso, JoaoManuelPaiva; Marques, Eduardo. "Towards a multi-softcore FPGA approach for the HOG algorithm". 2016.
    10.1109/INDIN.2016.7819144
  37. Holanda, JoseArnaldoMascagnide; Cardoso, JoaoManuelPaiva; Marques, Eduardo. "A pipelined multi-softcore approach for the HOG algorithm". 2016.
    10.1109/DASIP.2016.7853811
  38. Bispo, J; Reis, L; Cardoso, JMP. "C and OpenCL Generation from MATLAB". 2015.
    10.1145/2695664.2695911
  39. Silvano, C; Agosta, G; Bartolini, A; Beccari, A; Benini, L; Cardoso, JMP; Cavazzoni, C; et al. "ANTAREX - AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems". 2015.
    10.1109/cse.2015.58
  40. Paulino, N; Ferreira, JC; Bispo, J; Cardoso, JMP. "Transparent Acceleration of Program Execution Using Reconfigurable Hardware". 2015.
  41. Nobre, R; Martins, LGA; Cardoso, JMP. "Use of previously acquired positioning of optimizations for phase ordering exploration". 2015.
    10.1145/2764967.2764978
  42. Bispo, J; Reis, L; Cardoso, JMP. "Techniques for efficient MATLAB-to-C compilation". 2015.
    10.1145/2774959.2774961
  43. Azarian, A; Cardoso, JMP. "Reducing Misses to External Memory Accesses in Task-Level Pipelining". 2015.
    10.1109/iscas.2015.7168910
  44. Leong, PHW; Amano, H; Anderson, J; Bertels, K; Cardoso, JMP; Diessel, O; Gogniat, G; et al. "Significant Papers from the First 25 Years of the FPL Conference". 2015.
    10.1109/FPL.2015.7293747
  45. Carvalho, T; Pinto, P; Cardoso, JMP. "Programming strategies for contextual runtime specialization". 2015.
    10.1145/2764967.2764973
  46. de Oliveira, CB; Menotti, R; Cardoso, JMP; Marques, E. "A Special-Purpose Language for Implementing Pipelined FPGA-based Accelerators". 2015.
    10.1109/FDL.2015.7306085
  47. Silvano, C.; Cardoso, J.M.P.; Huebner, M.. "Message from general and program chairs". 2014.
  48. Nobre, R.; Pinto, P.; Carvalho, T.; Cardoso, J.M.P.; Diniz, P.C.. "On expressing strategies for directive-driven multicore programing models". 2014.
    10.1145/2556863.2556870
  49. De Oliveira, C.B.; Cardoso, J.M.P.; Marques, E.. "High-level synthesis from C vs. a DSL-based approach". 2014.
    10.1109/IPDPSW.2014.34
  50. Paulino, N.M.C.; Ferreira, J.C.; Cardoso, J.M.P.. "Trace-based reconfigurable acceleration with data cache and external memory support". 2014.
    10.1109/ispa.2014.29
  51. Martins, L.G.A.; Nobre, R.; Delbem, A.C.B.; Marques, E.; Cardoso, J.M.P.. "A clustering-based approach for exploring sequences of compiler optimizations". 2014.
    10.1109/CEC.2014.6900634
  52. Bispo, J.; Reis, L.; Cardoso, J.M.P.. "Multi-target c code generation from MATLAB". 2014.
    10.1145/2627373.2627389
  53. Paulino, N.; Ferreira, J.C.; Cardoso, J.M.P.. "Architecture for transparent binary acceleration of loops with memory accesses". 2013.
    10.1007/978-3-642-36812-7_12
  54. Coutinho, J.G.F.; Cardoso, J.M.P.; Carvalho, T.; Nobre, R.; Bhattacharya, S.; Diniz, P.C.; Fitzpatrick, L.; Nane, R.. "Deriving resource efficient designs using the REFLECT aspect-oriented approach (extended abstract)". 2013.
    10.1007/978-3-642-36812-7_29
  55. Petrov, Z.; Zaykov, P.G.; Cardoso, J.M.P.; Coutinho, J.G.F.; Diniz, P.C.; Luk, W.. "An aspect-oriented approach for designing safety-critical systems". 2013.
    10.1109/AERO.2013.6497184
  56. Al Farisi, B.; Bruneel, K.; Cardoso, J.M.P.; Stroobandt, D.. "An automatic tool flow for the combined implementation of multi-mode circuits". 2013.
  57. Azarian, A.; Cardoso, J.M.P.; Werner, S.; Becker, J.. "An FPGA-based multi-core approach for pipelining computing stages". 2013.
    10.1145/2480362.2480647
  58. Santos, A.C.; Cardoso, J.M.P.; Diniz, P.C.; Ferreira, D.R.. "Specifying adaptations through a DSL with an application to mobile robot navigation". 2013.
    10.4230/OASIcs.SLATE.2013.219
  59. Bispo, J.; Pinto, P.; Nobre, R.; Carvalho, T.; Cardoso, J.M.P.; Diniz, P.C.. "The MATISSE MATLAB compiler: A MATrix(MATLAB)-aware compiler InfraStructure for embedded computing SystEms". 2013.
    10.1109/INDIN.2013.6622952
  60. Cardoso, J.M.P.. "General chair message". 2013.
    10.1109/FPL.2013.6645485
  61. Martins, P.; Lopes, P.; Fernandes, J.P.; Saraiva, J.; Cardoso, J.M.P.. "Program and aspect metrics for MATLAB". 2012.
    10.1007/978-3-642-31128-4_16
  62. Cardoso, J.M.P.; Carvalho, T.; Coutinho, J.G.F.; Luk, W.; Nobre, R.; Diniz, P.C.; Petrov, Z.. "LARA: An aspect-oriented programming language for embedded systems". 2012.
    10.1145/2162049.2162071
  63. Coutinho, J.G.F.; Carvalho, T.; Durand, S.; Cardoso, J.M.P.; Nobre, R.; Diniz, P.C.; Luk, W.. "Experiments with the LARA aspect-oriented approach". 2012.
    10.1145/2162110.2162129
  64. Bispo, J.; Cardoso, J.M.P.; Monteiro, J.. "Hardware pipelining of runtime-detected loops". 2012.
  65. Cardoso, J.M.P.; Teixeira, J.; Alves, J.C.; Nobre, R.; Diniz, P.C.; Coutinho, J.G.F.; Luk, W.. "Specifying compiler strategies for FPGA-based systems". 2012.
    10.1109/FCCM.2012.41
  66. Coutinho, J.G.F.; Bhattacharya, S.; Luk, W.; Constantinides, G.A.; Cardoso, J.M.P.; Carvalho, T.; Diniz, P.C.; Petrov, Z.. "Resource-efficient designs using an aspect-oriented approach". 2012.
    10.1109/ICCSE.2012.62
  67. Cardoso, J.M.P.. "Programming strategies for runtime adaptability". 2012.
    10.1109/ReCoSoC.2012.6322875
  68. Azarian, A.; Ferreira, J.C.; Werner, S.; Petrov, Z.; Cardoso, J.M.P.; Huebner, M.. "Analysis of error detection schemes: Toolchain support and hardware/software implications". 2012.
    10.1109/AHS.2012.6268670
  69. Cardoso, J.M.P.; Carvalho, T.; Coutinho, J.G.F.; Diniz, P.C.; Petrov, Z.; Luk, W.. "Controlling hardware synthesis with aspects". 2012.
    10.1109/DSD.2012.33
  70. Cardoso, J.M.P.; Carvalho, T.; Teixeira, J.; Diniz, P.C.; Goncalves, F.; Petrov, Z.. "Hardware/software specialization through aspects: The LARA approach". 2012.
    10.1109/SAMOS.2012.6404183
  71. Almeida, João Paulo A.; Cardoso, Evellin C. S.. "On the elements of an enterprise". 2011.
    10.1145/1982185.1982256
  72. Bispo, J.; Cardoso, J.M.P.. "Techniques for dynamically mapping computations to coprocessors". 2011.
    10.1109/ReConFig.2011.86
  73. Sanches, A.; Cardoso, J.M.P.; Delbem, A.C.B.. "Identifying merge-beneficial software kernels for hardware implementation". 2011.
    10.1109/ReConFig.2011.51
  74. Bispo, J.; Paulino, N.; Cardoso, J.M.P.; Ferreira, J.C.. "From instruction traces to specialized reconfigurable arrays". 2011.
    10.1109/ReConFig.2011.43
  75. Petrov, Z.; Kratky, K.; Cardoso, J.M.P.; Diniz, P.C.. "Programming safety requirements in the REFLECT design flow". 2011.
    10.1109/INDIN.2011.6035002
  76. Santos, A.C.; Diniz, P.C.; Cardoso, J.M.P.; Ferreira, D.R.. "A domain-specific language for the specification of adaptable context inference". 2011.
    10.1109/EUC.2011.4
  77. João Bispo; João Canas Ferreira; Nuno Paulino; João M.P. Cardoso. "From Instruction Traces to Specialized Reconfigurable Arrays". 2011.
  78. João Bispo; João Canas Ferreira; Nuno Paulino; João M.P. Cardoso. "From Instruction Traces to Specialized Reconfigurable Arrays". 2011.
  79. Bispo, J.; Cardoso, J.M.P.. "On identifying and optimizing instruction sequences for dynamic compilation". 2010.
    10.1109/FPT.2010.5681454
  80. Bispo, J.; Cardoso, J.M.P.. "On identifying segments of traces for dynamic compilation". 2010.
    10.1109/FPL.2010.61
  81. Rosado, A.; Cardoso, J.M.P.. "A query processing strategy for conceptual queries based on object-role modeling". 2010.
    10.1109/NSS.2010.85
  82. Menotti, R.; Cardoso, J.M.P.; Fernandes, M.M.; Marques, E.. "On using LALP to map an audio encoder/decoder on FPGAs". 2010.
    10.1109/ISIE.2010.5637845
  83. Becker, J.; Bozorgzadeh, E.; Cardoso, J.M.P.; Dasu, A.. "Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010: Welcome message". 2010.
    10.1109/IPDPSW.2010.5470681
  84. Sanches, A.; Cardoso, J.M.P.. "On identifying patterns in code repositories to assist the generation of hardware templates". 2010.
    10.1109/FPL.2010.62
  85. Santos, A.C.; Tarrataca, L.; Cardoso, J.M.P.. "An analysis of navigation algorithms for smartphones using J2ME". 2009.
    10.1007/978-3-642-01802-2_20
  86. Santos, A.C.; Tarrataca, L.; Cardoso, J.M.P.; Ferreira, D.R.; Diniz, P.C.; Chainho, P.. "Context inference for mobile applications in the UPCASE project". 2009.
    10.1007/978-3-642-01802-2_26
  87. Santos, A.C.; Cardoso, J.M.P.; Ferreira, D.R.; Diniz, P.C.. "Mobile context provider for social networking". 2009.
    10.1007/978-3-642-05290-3_59
  88. Ferreira, R.; Damiany, A.; Vendramini, J.; Teixeira, T.; Cardoso, J.M.P.. "On simplifying placement and routing by extending coarse-grained reconfigurable arrays with omega networks". 2009.
    10.1007/978-3-642-00641-8_16
  89. Tarrataca, L.; Santos, A.C.; Cardoso, J.M.P.. "The current feasibility of gesture recognition for a smartphone using J2ME". 2009.
    10.1145/1529282.1529652
  90. Menotti, R.; Cardoso, J.M.P.; Fernandes, M.M.; Marques, E.. "Automatic generation of FPGA hardware accelerators using a domain specific language". 2009.
    10.1109/FPL.2009.5272485
  91. Menotti, R.; Cardoso, J.M.P.; Fernandes, M.M.; Marques, E.. "LALP: A novel language to program custom FPGA-based architectures". 2009.
    10.1109/SBAC-PAD.2009.23
  92. Marcelino, R.; Neto, H.C.; Cardoso, J.M.P.. "Unbalanced FIFO sorting for FPGA-Based systems". 2009.
    10.1109/ICECS.2009.5410898
  93. Marcelino, R.; Neto, H.C.; Cardoso, J.M.P.. "A comparison of three representative hardware sorting units". 2009.
    10.1109/IECON.2009.5415409
  94. Marcelino, R.; Neto, H.; Cardoso, J.M.P.. "Sorting units for FPGA-Based embedded systems". 2008.
    10.1007/978-0-387-09661-2_2
  95. Bechini, A.; Prete, C.A.; Altenbernd, P.; Bartolini, S.; Bertin, V.; Buttazzo, G.; Cardoso, J.M.P.; et al. "Special track on embedded systems: Applications, solutions, and techniques". 2008.
    10.1145/1363686.1364033
  96. Morra, C.; Cardoso, J.M.P.; Bispo, J.; Becker, J.. "Retargeting, evaluating, and generating reconfigurable array-based architectures". 2008.
    10.1109/SASP.2008.4570783
  97. Morra, C.; Bispo, J.; Cardoso, J.M.P.; Becke, J.. "Combining rewriting-logic, architecture generation, and simulation to exploit coarse-grained reconfigurable architectures". 2008.
    10.1109/FCCM.2008.37
  98. Bispo, J.; Sourdis, I.; Cardoso, J.M.P.; Vassiliadis, S.. "Synthesis of regular expressions targeting FPGAs: Current status and open issues". 2007.
  99. Lima, J.; Menotti, R.; Cardoso, J.M.P.; Marques, E.. "A methodology to design FPGA-based PID controllers". 2007.
    10.1109/ICSMC.2006.385252
  100. Ferreira, R.; Garcia, A.; Teixeira, T.; Cardoso, J.M.P.. "A polynomial placement algorithm for data driven coarse-grained reconfigurable architectures". 2007.
    10.1109/ISVLSI.2007.14
  101. Menotti, R.; Marques, E.; Cardoso, J.M.P.. "Aggressive loop pipelining for reconfigurable architectures". 2007.
    10.1109/FPL.2007.4380699
  102. De Holanda, J.A.; Assumpção Jr., J.; Wolf, D.F.; Marques, E.; Cardoso, J.M.P.. "On adapting power estimation models for embedded soft-core processors". 2007.
    10.1109/SIES.2007.4297358
  103. Morra, C.; Cardoso, J.M.P.; Becker, J.. "Using rewriting logic to match patterns of instructions from a compiler intermediate form to coarse-grained processing elements". 2007.
    10.1109/IPDPS.2007.370369
  104. Rodrigues, R.; Cardoso, J.M.P.; Diniz, P.C.. "A data-driven approach for pipelining sequences of data-dependent loops". 2007.
    10.1109/FCCM.2007.16
  105. Bonato, V.; Peron, R.; Wolf, D.F.; De Holanda, J.A.M.; Marques, E.; Cardoso, J.M.P.. "An FPGA implementation for a Kalman filter with application to mobile robotics". 2007.
    10.1109/SIES.2007.4297329
  106. Bispo, J.; Sourdis, I.; Cardoso, J.M.P.; Vassiliadis, S.. "Regular expression matching for reconfigurable packet inspection". 2006.
    10.1109/FPT.2006.270302
  107. Lopes, J.J.; Silva, J.L.E.; Marques, E.; Cardoso, J.M.P.. "A benchmark approach for compilers in reconfigurable hardware". 2006.
    10.1109/IWSOC.2006.348220
  108. Da Silva, M.V.; Ferreira, R.; Garcia, A.; Cardoso, J.M.P.. "Mesh mapping exploration for coarse-grained reconfigurable array architectures". 2006.
    10.1109/RECONF.2006.307749
  109. Silva, P.; Azevedo, A.; Toscano, C.; Cardoso, J.. "An innovative approach in supporting the operation of complex equipment machinery: The KoBaS Project case". 2006.
  110. Cardoso, J.M.P.. "New challenges in computer science education". 2005.
    10.1145/1067445.1067502
  111. Cardoso, J.M.P.. "On estimations for compiling software to FPGA-based systems". 2005.
    10.1109/ASAP.2005.47
  112. Rodrigues, R.; Cardoso, J.M.P.. "Pipelining sequences of loops: A first example". 2005.
  113. Rodrigues, R.M.M.; Cardoso, J.M.P.. "A test infrastructure for compilers targeting FPGAs". 2005.
  114. Rodrigues, R.; Cardoso, J.M.P.. "An infrastructure to functionally test designs generated by compilers targeting FPGAs". 2005.
    10.1109/DATE.2005.60
  115. Cardoso, J.M.P.. "CHIADO - Compilation of high-level computationally intensive algorithms to dynamically reconfigurable computing systems". 2005.
    10.1117/12.608805
  116. Cardoso, J.M.P.. "Data-driven array architectures: A rebirth?". 2005.
    10.1117/12.608799
  117. Ferreira, R.; Cardoso, J.M.P.; Toledo, A.; Neto, H.C.. "Data-driven regular reconfigurable arrays: Design space exploration and mapping". 2005.
  118. Cardoso, J.M.P.. "Dynamic loop pipelining in data-driven architectures". 2005.
    10.1145/1062261.1062283
  119. Bechini, A.; Bodin, F.; Prete, C.A.; Bartolini, S.; Buttazzo, G.; Cardoso, J.M.P.; Dang, T.; et al. "Editorial message for the special track on embedded systems: Applications, solutions, and techniques". 2005.
    10.1145/1066677.1066869
  120. Cardoso, João M. P.. "New challenges in computer science education". 2005.
    10.1145/1151954.1067502
  121. Cardoso, J.M.P.. "Self-loop pipelining and reconfigurable dataflow arrays". 2004.
  122. Cardoso, J.M.P.; Diniz, P.C.. "Modeling loop unrolling: Approaches and open issues". 2004.
  123. Gonçalves, R.A.; Moraes, P.A.; Cardoso, J.M.P.; Wolf, D.F.; Fernandes, M.M.; Romero, R.A.F.; Marques, E.. "ARCHITECT-R: A system for reconfigurable robots design". 2003.
  124. Cardoso, J.M.P.; Weinhardt, M.. "From C programs to the configure-execute model". 2003.
    10.1109/DATE.2003.1253670
  125. Cardoso, J.M.P.; Weinhardt, M.. "XPP-VC: A C Compiler with temporal partitioning for the PACT-XPP architecture". 2002.
    10.1007/3-540-46117-5_89
  126. Cardoso, J.M.P.; Neto, H.C.. "Macro-based hardware compilation of Java™ bytecodes into a dynamic reconfigurable computing system". 1999.
  127. Cardoso, Joao M.P.; Neto, Horacio C.. "Towards an automatic path from JavaTM bytecodes to hardware through high-level synthesis". 1998.
    10.1109/ICECS.1998.813276
Artigo em revista
  1. Pinto, P; Bispo, J; Cardoso, J; Barbosa, JG; Gadioli, D; Palermo, G; Martinovic, J; et al. "Pegasus: Performance Engineering for Software Applications Targeting HPC Systems". IEEE TRANSACTIONS ON SOFTWARE ENGINEERING (2022):
    10.1109/tse.2020.3001257
  2. Ayesha Gauhar; Adnan Rashid; Osman Hasan; João Bispo; João M.P. Cardoso. "Formal verification of Matrix based MATLAB models using interactive theorem proving". PeerJ Computer Science (2021): https://doi.org/10.7717/peerj-cs.440.
    10.7717/peerj-cs.440
  3. Garcia, KD; de Sa, CR; Poel, M; Carvalho, T; Mendes Moreira, J; Cardoso, JMP; de Carvalho, ACPLF; Kok, JN. "An ensemble of autonomous auto-encoders for human activity recognition". NEUROCOMPUTING (2021):
    10.1016/j.neucom.2020.01.125
  4. Paulino, N; Bispo, J; Ferreira, JC; Cardoso, JMP. "A Binary Translation Framework for Automated Hardware Generation". IEEE MICRO (2021):
    10.1109/mm.2021.3088670
  5. Paulo J. S. Ferreira; João M. P. Cardoso; João Mendes-Moreira. "kNN Prototyping Schemes for Embedded Human Activity Recognition with Online Learning". Computers 9 4 (2020): 96-96. https://doi.org/10.3390/computers9040096.
    10.3390/computers9040096
  6. Carlos Alberto Oliveira de Souza Junior; João Bispo; João M. P. Cardoso; Pedro C. Diniz; Eduardo Marques. "Exploration of FPGA-Based Hardware Designs for QR Decomposition for Solving Stiff ODE Numerical Methods Using the HARP Hybrid Architecture". Electronics 9 5 (2020): 843-843. https://doi.org/10.3390/electronics9050843.
    10.3390/electronics9050843
  7. Reis, L.; Bispo, J.; Cardoso, J.M.P.. "Compilation of MATLAB computations to CPU/GPU via C/OpenCL generation". Concurrency Computation (2020): http://www.scopus.com/inward/record.url?eid=2-s2.0-85085710813&partnerID=MN8TOARS.
    10.1002/cpe.5854
  8. Paulino, N; Ferreira, JC; Cardoso, JMP. "Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets". IEEE ACCESS (2020):
    10.1109/access.2020.3017552
  9. Paulino, N; Ferreira, JC; Cardoso, JMP. "Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey". ACM Comput. Surv. (2020):
    10.1145/3369764
  10. Bispo, J; Cardoso, JMP. "Clava: C/C plus plus source-to-source compilation using LARA". SOFTWAREX (2020):
    10.1016/j.softx.2020.100565
  11. Nuno M. C. Paulino; Joao Canas Ferreira; Joao M. P. Cardoso. "Dynamic Partial Reconfiguration of Customized Single-Row Accelerators". IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2019): 1-10. https://doi.org/10.1109/TVLSI.2018.2874079.
    10.1109/TVLSI.2018.2874079
  12. Besnard, L; Pinto, P; Lasri, I; Bispo, J; Rohou, E; Cardoso, JMP. "A framework for automatic and parameterizable memoization". SoftwareX (2019):
    10.1016/j.softx.2019.100322
  13. Silvano, C; Agosta, G; Bartolini, A; Beccari, AR; Benini, L; Besnard, L; Bispo, J; et al. "The ANTAREX domain specific language for high performance computing". MICROPROCESSORS AND MICROSYSTEMS (2019):
    10.1016/j.micpro.2019.05.005
  14. Nobre, R; Bispo, J; Carvalho, T; Cardoso, JMP. "Nonio - modular automatic compiler phase selection and ordering specialization framework for modern compilers". SOFTWAREX (2019):
    10.1016/j.softx.2019.100238
  15. Arabnejad, H; Bispo, J; Cardoso, JMP; Barbosa, JG. "Source-to-source compilation targeting OpenMP-based automatic parallelization of C applications". Journal of Supercomputing (2019):
    10.1007/s11227-019-03109-9
  16. Vitali, E.; Gadioli, D.; Palermo, G.; Golasowski, M.; Bispo, J.; Pinto, P.; Martinovic, J.; et al. "An Efficient Monte Carlo-based Probabilistic Time-Dependent Routing Calculation Targeting a Server-Side Car Navigation System". IEEE Transactions on Emerging Topics in Computing (2019): http://www.scopus.com/inward/record.url?eid=2-s2.0-85069896045&partnerID=MN8TOARS.
    10.1109/TETC.2019.2919801
  17. Pedro Pinto; Tiago Carvalho; João Bispo; Miguel António Ramalho; João M.P. Cardoso. "Aspect composition for multiple target languages using LARA". Computer Languages, Systems & Structures 53 (2018): 1-26. https://doi.org/10.1016/j.cl.2017.12.003.
    10.1016/j.cl.2017.12.003
  18. Paulino, NMC; Ferreira, JC; Cardoso, JMP. "Dynamic Partial Reconfiguration of Customized Single-Row Accelerators". IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2018):
    10.1109/tvlsi.2018.2874079
  19. Leong, PHW; Amano, H; Anderson, J; Bertels, K; Cardoso, JMP; Diessel, O; Gogniat, G; et al. "The First 25 Years of the FPL Conference: Significant Papers". ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS (2017): https://www.authenticus.pt/P-00M-KY3.
    10.1145/2996468
  20. Bispo, Joao; Cardoso, JoaoM.P.. "A MATLAB subset to C compiler targeting embedded systems". Softw., Pract. Exper. (2017): https://www.authenticus.pt/P-00M-BFX.
    10.1002/spe.2408
  21. Paulino, NunoMiguelCardanha; Ferreira, JoaoCanas; Cardoso, JoaoM.P.. "Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces". IEEE Trans. VLSI Syst. (2017): https://www.authenticus.pt/P-00M-AM7.
    10.1109/tvlsi.2016.2573640
  22. Azarian, A; Cardoso, JMP. "Pipelining data-dependent tasks in FPGA-based multicore architectures". MICROPROCESSORS AND MICROSYSTEMS (2016): https://www.authenticus.pt/P-00K-BGG.
    10.1016/j.micpro.2016.02.008
  23. Martins, LGA; Nobre, R; Cardoso, JMP; Delbem, ACB; Marques, E. "Clustering-Based Selection for the Exploration of Compiler Optimization Sequences". ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION (2016): https://www.authenticus.pt/P-00K-AMZ.
    10.1145/2883614
  24. Nobre, R; Martins, LGA; Cardoso, JMP. "A Graph-Based Iterative Compiler Pass Selection and Phase Ordering Approach". ACM SIGPLAN NOTICES (2016): https://www.authenticus.pt/P-00K-H7V.
    10.1145/2907950.2907959
  25. Al Farisi, B; Heyse, K; Bruneel, K; Cardoso, J; Stroobandt, D. "Enabling FPGA routing configuration sharing in dynamic partial reconfiguration". DESIGN AUTOMATION FOR EMBEDDED SYSTEMS (2015): https://www.authenticus.pt/P-00G-D35.
    10.1007/s10617-014-9143-8
  26. Cardoso, J.M.P.; Coutinho, J.G.F.; Carvalho, T.; Diniz, P.C.; Petrov, Z.; Luk, W.; Gonçalves, F.. "Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach". Software - Practice and Experience (2015): http://www.scopus.com/inward/record.url?eid=2-s2.0-84920601843&partnerID=MN8TOARS.
    10.1002/spe.2301
  27. Martins, L.G.A.; Nobre, R.; Delbem, A.C.B.; Marques, E.; Cardoso, J.M.P.. "Exploration of compiler optimization sequences using clustering-based selection". ACM SIGPLAN Notices 49 5 (2014): 63-72. http://www.scopus.com/inward/record.url?eid=2-s2.0-84907019414&partnerID=MN8TOARS.
    10.1145/2597809.2597821
  28. Bonato, V.; Fernandes, M.M.; Cardoso, J.M.P.; Marques, E.. "Practical education fostered by research projects in an embedded systems course". International Journal of Reconfigurable Computing 2014 (2014): http://www.scopus.com/inward/record.url?eid=2-s2.0-84904606117&partnerID=MN8TOARS.
    10.1155/2014/287205
  29. Santos, A.C.; Cardoso, J.M.P.; Diniz, P.C.; Ferreira, D.R.; Petrov, Z.. "Specifying dynamic adaptations for embedded applications using a dsl". IEEE Embedded Systems Letters 6 3 (2014): 49-52. http://www.scopus.com/inward/record.url?eid=2-s2.0-84906834863&partnerID=MN8TOARS.
    10.1109/les.2014.2321325
  30. Santos, A.C.; Cardoso, J.M.P.; Diniz, P.C.; Ferreira, D.R.; Petrov, Z.. "A DSL for specifying run-time adaptations for embedded systems: an application to vehicle stereo navigation". Journal of Supercomputing 70 3 (2014): 1218-1248. http://www.scopus.com/inward/record.url?eid=2-s2.0-84919877597&partnerID=MN8TOARS.
    10.1007/s11227-014-1192-z
  31. Paulino, N.; Ferreira, J.C.; Cardoso, J.M.P.. "A reconfigurable architecture for binary acceleration of loops with memory accesses". ACM Transactions on Reconfigurable Technology and Systems 7 4 (2014): http://www.scopus.com/inward/record.url?eid=2-s2.0-84911387509&partnerID=MN8TOARS.
    10.1145/2629468
  32. Bispo, J.; Paulino, N.; Cardoso, J.M.P.; Ferreira, J.C.. "Transparent runtime migration of loop-based traces of processor instructions to reconfigurable processing units". International Journal of Reconfigurable Computing 2013 (2013): http://www.scopus.com/inward/record.url?eid=2-s2.0-84874864892&partnerID=MN8TOARS.
    10.1155/2013/340316
  33. Cardoso, J.M.P.; Carvalho, T.; Coutinho, J.G.F.; Nobre, R.; Nane, R.; Diniz, P.C.; Petrov, Z.; Luk, W.; Bertels, K.. "Controlling a complete hardware synthesis toolchain with LARA aspects". Microprocessors and Microsystems 37 8 PARTC (2013): 1073-1089. http://www.scopus.com/inward/record.url?eid=2-s2.0-84888297368&partnerID=MN8TOARS.
    10.1016/j.micpro.2013.06.001
  34. Cardoso, J.M.P.; Fernandes, J.M.; Monteiro, M.P.; Carvalho, T.; Nobre, R.. "Enriching MATLAB with aspect-oriented features for developing embedded systems". Journal of Systems Architecture 59 7 (2013): 412-428. http://www.scopus.com/inward/record.url?eid=2-s2.0-84886096762&partnerID=MN8TOARS.
    10.1016/j.sysarc.2013.04.003
  35. Bispo, J.; Cardoso, J.M.P.; Monteiro, J.. "Hardware pipelining of repetitive patterns in processor instruction traces". Journal of Integrated Circuits and Systems 8 1 (2013): 22-31. http://www.scopus.com/inward/record.url?eid=2-s2.0-84885355741&partnerID=MN8TOARS.
  36. Menotti, R.; Cardoso, J.M.P.; Fernandes, M.M.; Marques, E.. "LALP: A language to program custom FPGA-based acceleration engines". International Journal of Parallel Programming 40 3 (2012): 262-289. http://www.scopus.com/inward/record.url?eid=2-s2.0-84863614574&partnerID=MN8TOARS.
    10.1007/s10766-011-0187-0
  37. Ferreira, R.S.; Cardoso, J.M.P.; Damiany, A.; Vendramini, J.; Teixeira, T.. "Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks". Journal of Systems Architecture 57 8 (2011): 761-777. http://www.scopus.com/inward/record.url?eid=2-s2.0-79960696521&partnerID=MN8TOARS.
    10.1016/j.sysarc.2011.03.006
  38. Cardoso, J.M.P.; Diniz, P.; Weinhardt, M.. "Compiling for reconfigurable computing: A survey". ACM Computing Surveys 42 4 (2010): http://www.scopus.com/inward/record.url?eid=2-s2.0-77953948733&partnerID=MN8TOARS.
    10.1145/1749603.1749604
  39. Figo, D.; Diniz, P.C.; Ferreira, D.R.; Cardoso, J.M.P.. "Preprocessing techniques for context recognition from accelerometer data". Personal and Ubiquitous Computing 14 7 (2010): 645-662. http://www.scopus.com/inward/record.url?eid=2-s2.0-77957017939&partnerID=MN8TOARS.
    10.1007/s00779-010-0293-9
  40. Santos, A.C.; Cardoso, J.M.P.; Ferreira, D.R.; Diniz, P.C.; Chaínho, P.. "Providing user context for mobile and social networking applications". Pervasive and Mobile Computing 6 3 (2010): 324-341. http://www.scopus.com/inward/record.url?eid=2-s2.0-77955710544&partnerID=MN8TOARS.
    10.1016/j.pmcj.2010.01.001
  41. Santos, A.C.; Tarrataca, L.; Cardoso, J.M.P.. "The feasibility of navigation algorithms on smartphones using J2ME". Mobile Networks and Applications 15 6 (2010): 819-830. http://www.scopus.com/inward/record.url?eid=2-s2.0-78650681347&partnerID=MN8TOARS.
    10.1007/s11036-010-0236-8
  42. Cardoso, J.M.P.. "A teaching strategy for developing application specific architectures for FPGAs". International Journal of Engineering Education 24 4 (2008): 833-842. http://www.scopus.com/inward/record.url?eid=2-s2.0-51549083705&partnerID=MN8TOARS.
  43. Sourdis, I.; Bispo, J.; Cardoso, J.M.P.; Vassiliadis, S.. "Regular expression matching in reconfigurable hardware". Journal of Signal Processing Systems 51 1 (2008): 99-121. http://www.scopus.com/inward/record.url?eid=2-s2.0-43449132689&partnerID=MN8TOARS.
    10.1007/s11265-007-0131-0
  44. Bispo, J.; Cardoso, J.M.P.. "Synthesis of regular expressions for FPGAs". International Journal of Electronics 95 7 (2008): 685-704. http://www.scopus.com/inward/record.url?eid=2-s2.0-49149092746&partnerID=MN8TOARS.
    10.1080/00207210801924107
  45. Rodrigues, R.M.M.; Cardoso, J.M.P.. "On pipelining sequences of data-dependent loops". Journal of Universal Computer Science 13 3 (2007): 419-439. http://www.scopus.com/inward/record.url?eid=2-s2.0-34247842984&partnerID=MN8TOARS.
  46. Cardoso, J.M.P.; Constantinides, G.A.. "Applied reconfigurable computing". International Journal of Electronics 93 6 (2006): 347-348. http://www.scopus.com/inward/record.url?eid=2-s2.0-33744953736&partnerID=MN8TOARS.
    10.1080/00207210600562645
  47. Cardoso, J.M.P.; Neto, H.C.. "Compilation for FPGA-based reconfigurable hardware". IEEE Design and Test of Computers 20 2 (2003): 65-75. http://www.scopus.com/inward/record.url?eid=2-s2.0-0037341769&partnerID=MN8TOARS.
    10.1109/MDT.2003.1188264
  48. Cardoso, J.M.P.. "On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures". IEEE Transactions on Computers 52 10 (2003): 1362-1375. http://www.scopus.com/inward/record.url?eid=2-s2.0-0142039780&partnerID=MN8TOARS.
    10.1109/TC.2003.1234532
  49. Cardoso, João M. P.; Vestístias, Mário P.. "Architectures and compilers to support reconfigurable computing". Crossroads 5 3 (1999): 15⿿22-15⿿22. http://dx.doi.org/10.1145/331662.331672.
    10.1145/331662.331672
Capítulo de livro
  1. Julián Caba; João M. P. Cardoso; Fernando Rincón; Julio Dondo; Juan Carlos López. "Rapid Prototyping and Verification of Hardware Modules Generated Using HLS". 446-458. Springer International Publishing, 2018.
    10.1007/978-3-319-78890-6_36
  2. Paulino, N; Reis, L; Cardoso, JMP. "On Coding Techniques for Targeting FPGAs via OpenCL". 2018.
    10.3233/978-1-61499-843-3-652
  3. Cardoso, JoaoM.P.; Weinhardt, Markus. "High-Level Synthesis". 2016.
    10.1007/978-3-319-26408-0_2
  4. de Oliveira, CB; Menotti, R; Cardoso, JMP; Marques, E. "A Special-Purpose Language for Implementing Pipelined FPGA-Based Accelerators". 2016.
    10.1007/978-3-319-31723-6_4
  5. Azarian, A.; Cardoso, J.M.P.. "Coarse/fine-grained approaches for pipelining computing stages in fpga-based multicore architectures". 2013.
  6. Cardoso, J.M.P.; De F. Coutinho, J.G.; Diniz, P.C.. "Related work". 2013.
    10.1007/978-1-4614-4894-5-7
  7. Gonçalves, F.; Petrov, Z.; De F. Coutinho, J.G.; Nane, R.; Sima, V.-M.; Cardoso, J.M.P.; Werner, S.; et al. "LARA experiments". 2013.
    10.1007/978-1-4614-4894-5-6
  8. Diniz, P.C.; Cardoso, J.M.P.; De F. Coutinho, J.G.; Petrov, Z.. "Conclusions". 2013.
    10.1007/978-1-4614-4894-5-8
  9. Cardoso, J.M.P.; De F. Coutinho, J.G.; Nane, R.; Sima, V.-M.; Olivier, B.; Carvalho, T.; Nobre, R.; et al. "The REFLECT design-flow". 2013.
    10.1007/978-1-4614-4894-5-2
  10. Nobre, R.; Cardoso, J.M.P.; Olivier, B.; Nane, R.; Fitzpatrick, L.; De F. Coutinho, J.G.; Van Someren, H.; et al. "Hardware/software compilation". 2013.
    10.1007/978-1-4614-4894-5-5
  11. Cardoso, J.M.P.; De F. Coutinho, J.G.; Carvalho, T.; Diniz, P.C.. "The LARA language". 2013.
    10.1007/978-1-4614-4894-5-3
  12. De F. Coutinho, J.G.; Cardoso, J.M.P.; Carvalho, T.; Bhattacharya, S.; Luk, W.; Constantinides, G.; Diniz, P.C.; Petrov, Z.. "Aspect-based source to source transformations". 2013.
    10.1007/978-1-4614-4894-5-4
  13. Diniz, P.C.; Cardoso, J.M.P.; De F. Coutinho, J.G.; Petrov, Z.. "Introduction". 2013.
    10.1007/978-1-4614-4894-5-1
  14. Diniz, P.C.; Cardoso, J.M.P.. "Code transformations for embedded reconfigurable computing architectures". 2009.
    10.1007/978-3-642-18023-1_8
Edição de livro
  1. Bartolini, A; Cardoso, JMP; Silvano, C. Proceedings of the 2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, ANDARE@PACT 2018, Limassol, Cyprus, November 4, 2018. 2018.
  2. Bartolini, A; Cardoso, JMP; Silvano, C. Proceedings of the 1st Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, ANDARE@PACT 2017, Portland, OR, USA, September 9, 2017. 2017.
  3. Silvano, C; Cardoso, JMP; Agosta, G; Hübner, M. Proceedings of the 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 5th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2016, Prague, Czech Republic, January 18, 2016. 2016.
    10.1145/2872421
  4. Agosta, G; Silvano, C; Cardoso, JMP; Hübner, M. Proceedings of the 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 4th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2015, Amsterdam, Netherlands, January 21, 2015. 2015.
    10.1145/2701310
  5. Bozorgzadeh, E; Cardoso, JMP; Abreu, R; Memik, SO. 13th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2013, Porto, Portugal, October 21-23, 2015. 2015.
  6. Plessl, C; Baz, DE; Cong, G; Cardoso, JMP; Veiga, L; Rauber, T. 18th IEEE International Conference on Computational Science and Engineering, CSE 2015, Porto, Portugal, October 21-23, 2015. 2015.
  7. Silvano, C; Cardoso, JMP; Hübner, M. Proceedings of the 5th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 3rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2014, Vienna, Austria, January 20, 2014. 2014.
    10.1145/2556863
  8. Goehringer, D; Santambrogio, MD; Cardoso, JMP; Bertels, K. Reconfigurable Computing: Architectures, Tools, and Applications - 10th International Symposium, ARC 2014, Vilamoura, Portugal, April 14-16, 2014. Proceedings. 2014.
    10.1007/978-3-319-05960-0
  9. Cardoso, João. Reconfigurable Computing. 2011.
    10.1007/978-1-4614-0061-5_1
  10. Cardoso, João. Reconfigurable Computing: Architectures, Tools and Applications. 2007.
    10.1007/978-3-540-71431-6_17
  11. Cardoso, João. Reconfigurable Computing: Architectures and Applications. 2006.
    10.1007/11802839
Edição de número de revista
  1. Cardoso, J.M.P.; Diniz, P.C.; Morrow, K.. "Guest editorial FPL 2013". ACM Transactions on Reconfigurable Technology and Systems 8 2 (2015): http://www.scopus.com/inward/record.url?eid=2-s2.0-84929178744&partnerID=MN8TOARS.
    10.1145/2737805
  2. Dasu, A.; Cardoso, J.M.P.; Bozorgzadeh, E.; Becker, J.. "Selected papers from the 17th reconfigurable architectures workshop (RAW2010)". International Journal of Reconfigurable Computing 2011 (2011): http://www.scopus.com/inward/record.url?eid=2-s2.0-80052660309&partnerID=MN8TOARS.
    10.1155/2011/574972
  3. Cardoso, J.M.P.; Diniz, P.C.. "IJE special issue on reconfigurable hardware systems". International Journal of Electronics 95 7 (2008): http://www.scopus.com/inward/record.url?eid=2-s2.0-49549103348&partnerID=MN8TOARS.
    10.1080/00207210801924461
Livro
  1. Cardoso, J.M.P.; Coutinho, J.G.F.; Diniz, P.C.. Embedded Computing for High Performance: Efficient Mapping of Computations Using Customization, Code Transformations and Compilation. 2017.
  2. Cardoso, João M.P.; Diniz, Pedro C.. Compilation Techniques for Reconfigurable Architectures. Springer US. 2009.
    10.1007/978-0-387-09671-1_6
  3. Azevedo, A.; Silva, P.; Toscano, C.; Cardoso, J.. An innovative maintenance solution for complex machinery: The Kobas Project Case. 2006.
    10.1007/978-0-387-36594-7_26
Prefácio / Posfácio
  1. Bertels, K.; Cardoso, J.; Vassiliadis, S.. "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics): Preface". 2006.
Tese / Dissertação
  1. Erinaldo da Silva Pereira. "Um framework para coprojeto de hardware/software para o módulo da dinâmica do modelo brasileiro de previsão do tempo - BRAMS". Doutoramento, 2018. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-27032019-145106/.
  2. Leandro Andrade Martinez. "Um framework para coprojeto de hardware e software de sistemas avançados de assistência ao motorista baseados em câmeras". Doutoramento, 2017. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-06122017-104613/.
  3. Renê de Souza Pinto. "Caracterização do perfil de utilização de recursos de programas a partir de arquivos executáveis utilizando mineração de dados". Doutoramento, 2017. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-06022018-150306/.
  4. Renê de Souza Pinto. "Caracterização do perfil de utilização de recursos de programas a partir de arquivos executáveis utilizando mineração de dados". Doutoramento, 2017. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-06022018-150306/.
  5. Leandro Andrade Martinez. "Um framework para coprojeto de hardware e software de sistemas avançados de assistência ao motorista baseados em câmeras". Doutoramento, 2017. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-06122017-104613/.
  6. Luiz Gustavo Almeida Martins. "Exploração de sequências de otimização do compilador baseada em técnicas hibridas de mineração de dados complexos". Doutoramento, 2015. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-28032016-160827/.
  7. Cristiano Bacelar de Oliveira. "LALP+ : um framework para o desenvolvimento de aceleradores de hardware em FPGAs". Doutoramento, 2015. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-30082016-160232/.
  8. Luiz Gustavo Almeida Martins. "Exploração de sequências de otimização do compilador baseada em técnicas hibridas de mineração de dados complexos". Doutoramento, 2015. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-28032016-160827/.
  9. Maikon Adiles Fernandez Bueno. "Co-projeto de hardware e software de um escalonador de processos para arquiteturas multicore heterogêneas baseadas em computação reconfigurável". Doutoramento, 2013. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-29012014-105417/.
  10. Maikon Adiles Fernandez Bueno. "Co-projeto de hardware e software de um escalonador de processos para arquiteturas multicore heterogêneas baseadas em computação reconfigurável". Doutoramento, 2013. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-29012014-105417/.
  11. Pinto, Pedro Miguel dos Santos. "Suggesting loop unrolling using a heuristic-guided approach". Mestrado, 2012. oai:digitool.fe.up.pt:245828.
  12. Pinto, Pedro Miguel dos Santos. "Suggesting loop unrolling using a heuristic-guided approach". Mestrado, 2012. http://hdl.handle.net/10216/65579.
  13. Leandro Andrade Martinez. "Projeto de um sistema embarcado de predição de colisão e pedestres baseado em computação reconfigurável". Mestrado, 2011. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-27022012-110356/.
  14. Paulino, Nuno Miguel Cardanha. "Generation of reconfigurable circuits from machine code". Mestrado, 2011. oai:digitool.fe.up.pt:235463.
  15. Carvalho, Tiago Diogo Ribeiro de. "A meta-language and framework for aspect-oriented programming". Mestrado, 2011. oai:digitool.fe.up.pt:239019.
  16. Carvalho, Tiago Diogo Ribeiro de. "A meta-language and framework for aspect-oriented programming". Mestrado, 2011. http://hdl.handle.net/10216/63339.
  17. Paulino, Nuno Miguel Cardanha. "Generation of reconfigurable circuits from machine code". Mestrado, 2011. http://hdl.handle.net/10216/61292.
  18. Leandro Andrade Martinez. "Projeto de um sistema embarcado de predição de colisão e pedestres baseado em computação reconfigurável". Mestrado, 2011. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-27022012-110356/.
  19. Ricardo Menotti. "LALP: uma linguagem para exploração do paralelismo de loops em computação reconfigurável". Doutoramento, 2010. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-17082010-151100/.
  20. Ricardo Menotti. "LALP: uma linguagem para exploração do paralelismo de loops em computação reconfigurável". Doutoramento, 2010. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-17082010-151100/.
  21. Órfão, Tiago Miguel dos Reis. "Conversão assistida de código específico a um browser para outros browsers". Mestrado, 2009. oai:digitool.fe.up.pt:227589.
  22. Pires, Luis Rafael Roma da Câmara. "iFAct Recoding". Mestrado, 2009. oai:digitool.fe.up.pt:58199.
  23. Silva, Filipe Manuel Gomes. "Ferramenta de ofuscação de código Javascript". Mestrado, 2009. oai:digitool.fe.up.pt:228338.
  24. Jecel Mattos de Assumpção Júnior. "Projeto de um sistema de desvio de obstáculos para robôs móveis baseado em computação reconfigurável". Mestrado, 2009. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-30032010-092432/.
  25. Reis, Manuel Luís Campos. "Robô com unidade principal de processamento implementada em FPGAs". Mestrado, 2009. oai:digitool.fe.up.pt:145242.
  26. Pinho, Hugo Manuel Zenha de. "Aplicação de registo de ocorrências para dispositivos móveis". Mestrado, 2009. oai:digitool.fe.up.pt:228328.
  27. Costa, Tiago José Rocha Alves da. "Methods for dynamic identification of program control-flow structures for FPGA-based systems". Mestrado, 2009. oai:digitool.fe.up.pt:145246.
  28. Órfão, Tiago Miguel dos Reis. "Conversão assistida de código específico a um browser para outros browsers". Mestrado, 2009. http://hdl.handle.net/10216/58028.
  29. Reis, Manuel Luís Campos. "Robô com unidade principal de processamento implementada em FPGAs". Mestrado, 2009. http://hdl.handle.net/10216/58849.
  30. Jecel Mattos de Assumpção Júnior. "Projeto de um sistema de desvio de obstáculos para robôs móveis baseado em computação reconfigurável". Mestrado, 2009. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-30032010-092432/.
  31. Silva, Filipe Manuel Gomes. "Ferramenta de ofuscação de código Javascript". Mestrado, 2009. http://hdl.handle.net/10216/66712.
  32. Pinho, Hugo Manuel Zenha de. "Aplicação de registo de ocorrências para dispositivos móveis". Mestrado, 2009. http://hdl.handle.net/10216/61885.
  33. Pires, Luis Rafael Roma da Câmara. "iFAct Recoding". Mestrado, 2009. http://hdl.handle.net/10216/66815.
  34. Teixeira, Tiago Aparecido. "Heurísticas para a geração de arquiteturas reconfiguráveis em arranjos bidimensionais". Mestrado, 2009. http://locus.ufv.br/handle/123456789/2595.
  35. Costa, Tiago José Rocha Alves da. "Methods for dynamic identification of program control-flow structures for FPGA-based systems". Mestrado, 2009. http://hdl.handle.net/10216/58215.
  36. Marcelo Carvalho Sacchetin. "Análise e implementação de algoritmos para localização e mapeamento de robôs móveis baseada em computação reconfigurável\"". Mestrado, 2006. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-22082014-143916/.
  37. Marcelo Carvalho Sacchetin. "Análise e implementação de algoritmos para localização e mapeamento de robôs móveis baseada em computação reconfigurável\"". Mestrado, 2006. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-22082014-143916/.

Outros

Outra produção
  1. Guest Editorial: IEEE TC Special Section on Compiler Optimizations for FPGA-Based Systems. 2021. Cardoso, JMP; DeHon, A; Pozzi, L.
    10.1109/tc.2021.3117316
  2. Message from the symposium general chair and program chairs. 2019. Shibata, Y; Cardoso, JMP; Takamaeda Yamazaki, S.
  3. An Efficient Monte Carlo-based Probabilistic Time-Dependent Routing Calculation Targeting a Server-Side Car Navigation System. 2019. Vitali, E; Gadioli, D; Palermo, G; Golasowski, M; Bispo, J; Pinto, P; Martinovic, J; et al.
  4. The ANTAREX Domain Specific Language for High Performance Computing. 2019. Silvano, C; Agosta, G; Bartolini, A; Beccari, AR; Benini, L; Besnard, L; Bispo, J; et al.
  5. Compiler Phase Ordering as an Orthogonal Approach for Reducing Energy Consumption. 2018. Nobre, R; Reis, L; Cardoso, JMP.
  6. Improving OpenCL Performance by Specializing Compiler Phase Selection and Ordering. 2018. Nobre, R; Reis, L; Cardoso, JMP.
  7. A Preliminary Study on Hyperparameter Configuration for Human Activity Recognition. 2018. Garcia, KD; Carvalho, T; Moreira, JM; Cardoso, JMP; de Carvalho, ACPLF.
  8. Message from Andare’18 general and program chairs. 2018. Bartolini, A; Cardoso, JMP; Silvano, C.
  9. Introduction to the Special Section on FPL 2015. 2017. Cardoso, JMP; Silvano, C. https://www.authenticus.pt/P-00M-NW7.
    10.1145/3041224
  10. Recent advances in computational science and engineering research. 2017. Veiga, L; El Baz, D; Cardoso, JMP.
    10.1016/j.jocs.2017.09.012
  11. Foreword to the special issue of the 18th IEEE international conference on computational science and engineering (CSE2015). 2017. Plessl, C; Cong, GJ; Cardoso, JMP. https://www.authenticus.pt/P-00M-HNC.
    10.1002/cpe.4102
  12. Foreword to the Special Section on Reconfigurable Computing. 2017. Derrien, S; Atasu, K; Cardoso, JMP; Becker, J. https://www.authenticus.pt/P-00M-KT0.
    10.1007/s11265-017-1237-7
  13. Message from general and program co-chairs. 2017. Cardoso, JMP; Huebner, M; Agosta, G; Silvano, C. https://www.authenticus.pt/P-00M-N06.
  14. Special issue on design of algorithms and architectures for signal and image processing. 2017. Gorgon, M; Cardoso, JMP; Goehringer, D; Indrusiak, LS.
    10.1016/j.sysarc.2017.06.002
  15. Introduction to the special issue on architecture of computing systems. 2017. Hannig, F; Cardoso, JMP; Fey, D.
    10.1016/j.sysarc.2017.04.003
  16. Message from the EUC 2015 general chairs. 2015. Bozorgzadeh, E; Cardoso, JMP. https://www.authenticus.pt/P-00K-DR2.
    10.1109/euc.2015.4
  17. Fault Detection in C Programs using Monitoring of Range Values: Preliminary Results. 2015. Pinto, P; Abreu, R; Cardoso, JMP. https://www.authenticus.pt/P-00G-6BD.
  18. SPECIAL SECTION ON THE 2014 INTERNATIONAL SYMPOSIUM ON APPLIED RECONFIGURABLE COMPUTING. 2015. Goehringer, D; Santambrogio, MD; Cardoso, JMP; Bertels, K. https://www.authenticus.pt/P-00K-0DJ.
    10.1145/2831431
  19. Representation of Evolutionary Algorithms in FPGA Cluster for Project of Large-Scale Networks. 2014. Perina, AB; Gois, MM; Matias, P; Cardoso, JMP; Delbem, ACB; Bonato, V. https://www.authenticus.pt/P-00G-6BC.
  20. Conclusions. Compilation and Synthesis for Embedded Reconfigurable Systems. 2013. Diniz, Pedro C.; Cardoso, João M. P.; F. Coutinho, José Gabriel; Petrov, Zlatko. http://dx.doi.org/10.1007/978-1-4614-4894-5_8.
    10.1007/978-1-4614-4894-5_4
  21. Compilation and Temporal Partitioning for a Coarse-grain Reconfigurable Architecture. New Algorithms, Architectures and Applications for Reconfigurable Computing. 2005. Cardoso, João M.P.; Weinhardt, Markus. http://dx.doi.org/10.1007/1-4020-3128-9_9.
    10.1007/1-4020-3128-9_9
  22. Introduction. Lecture Notes in Computer Science. 2005. Gama, João; Moura-Pires, João; Cardoso, Margarida; Marques, Nuno Cavalheiro; Cavique, Luís. http://dx.doi.org/10.1007/11595014_28.
    10.1007/11595014_28
  23. An Environment for Exploring Data-Driven Architectures. Lecture Notes in Computer Science. 2004. Ferreira, Ricardo; Cardoso, João M. P.; Neto, Horácio C.. http://dx.doi.org/10.1007/978-3-540-30117-2_119.
    10.1007/978-3-540-30117-2_119
  24. Self-loop Pipelining and Reconfigurable Dataflow Arrays. Lecture Notes in Computer Science. 2004. Cardoso, João M. P.. http://dx.doi.org/10.1007/978-3-540-27776-7_25.
    10.1007/978-3-540-27776-7_24
  25. XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture. Lecture Notes in Computer Science. 2002. Cardoso, João M.P.; Weinhardt, Markus. http://dx.doi.org/10.1007/3-540-46117-5_89.
    10.1007/3-540-46117-5_89
  26. Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines. Lecture Notes in Computer Science. 2001. Cardoso, João M. P.; Neto, Horácio C.. http://dx.doi.org/10.1007/3-540-44687-7_54.
    10.1007/3-540-44687-7_54
  27. An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs. VLSI: Systems on a Chip. 2000. Cardoso, João M. P.; Neto, Horácio C.. http://dx.doi.org/10.1007/978-0-387-35498-9_43.
    10.1007/978-0-387-35498-9_43
Atividades

Orientação

Título / Tema
Papel desempenhado 		Curso (Tipo)
Instituição / Organização
2019 - 2019 Acceleration of Applications with FPGA-Based Computing Machines: New DSL
Orientador
 Engenharia Informática e Computação (Mestrado)
Universidade do Porto Faculdade de Engenharia, Portugal
2019 - 2019 On Making Feasible Smartphone-Based Human Activity Recognition
Orientador
 Engenharia Informática e Computação (Mestrado)
Universidade do Porto Faculdade de Engenharia, Portugal
2019 - 2019 Automatic switching between video and audio according to user’s context
Orientador
 Engenharia Informática e Computação (Mestrado)
Universidade do Porto Faculdade de Engenharia, Portugal
2019 - 2019 Energy Efficient Smartphone-based Users Activity Classification
Orientador
 Engenharia Informática e Computação (Mestrado)
Universidade do Porto Faculdade de Engenharia, Portugal
2018 - 2018 Restructuring Software Code for High-Level Synthesis using a Graph-based Approach Targeting FPGAs
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade do Porto Faculdade de Engenharia, Portugal
2016 - 2016 RAVEN: a Node.js Static Metadata Extracting Solution for JavaScript Applications
Orientador
 Engenharia Informática e Computação (Mestrado)
Universidade do Porto Faculdade de Engenharia, Portugal
2016 - 2016 Exploiting JavaScript Birthmarking Techniques for Code Theft Detection
Orientador
 Engenharia Informática e Computação (Mestrado)
Universidade do Porto Faculdade de Engenharia, Portugal
2016 - 2016 Runtime-aware Compiler Optimizations for High-Performance Embedded Computing
Orientador
 Engenharia Informática (Doutoramento)
Universidade do Porto Faculdade de Engenharia, Portugal
2015 - 2015 Efficient target and application specific selection and ordering of compiler passes
Orientador
 Engenharia Informática (Doutoramento)
Universidade do Porto Faculdade de Engenharia, Portugal
2015 - 2015 Programming and mapping strategies for embedded computing runtime adaptability
Orientador
 Engenharia Informática (Doutoramento)
Universidade do Porto Faculdade de Engenharia, Portugal
2015 - 2015 Multitarget Compilation Techniques for Generating Efficient OpenCL Code from Matrix-Oriented Computations
Orientador
 Informática (Doutoramento)
Universidade do Porto Faculdade de Engenharia, Portugal
2014 - 2014 Advanced JavaScript Tracking and Analytics Solution
Orientador
 Engenharia Informática e Computação (Mestrado)
Universidade do Porto Faculdade de Engenharia, Portugal
2014 - 2014 Optimização e Geração de código OpenCL para computação embutida
Orientador
 Engenharia Informática e Computação (Mestrado)
Universidade do Porto Faculdade de Engenharia, Portugal
2014 - 2014 Optimizing Java Code for Mobile Computing: The Android Example
Orientador
 Engenharia Informática e Computação (Mestrado)
Universidade do Porto Faculdade de Engenharia, Portugal
2013 - 2013 Task-Level Pipelining in Configurable Multicore Architectures
Orientador
 Engenharia Informática (Doutoramento)
Universidade do Porto Faculdade de Engenharia, Portugal
2011 - 2011 techniques to suggest fpga-based hardware/software implementations
Orientador
 Engenharia Informática (Doutoramento)
Universidade do Porto Faculdade de Engenharia, Portugal
2009 - 2009 A DSL-based Approach for the Specification of Software Adaptations in Embedded Systems
Orientador
 Engenharia Informática e de Computadores (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2008 - 2008 Mapping Runtime-Detected Loops from Microprocessors to Reconfigurable Processing Units
Orientador
 Engenharia Informática e de Computadores (Doutoramento)
2006 - 2006 SORTING MACHINES FOR FPGA-BASED EMBEDDED SYSTEMS
Orientador
 Engenharia Electrotécnica e de Computadores (Doutoramento)
Distinções

Prémio

2016 IEEE Senior Member
2009 ACM Senior Member